The master device sends the slave address (7 bits) and the data direction bit (R/
W = 0).
The slave device sends an acknowledge signal if the slave address is correct.
The master device sends the control register address (8 bits).
The slave device sends an acknowledge signal.
The master device generates a repeated-start condition.
The master device sends the slave address (7 bits) and the data direction bit (R/
W = 1).
The slave device sends an acknowledge signal if the slave address is correct.
The slave device sends the data byte from the addressed register.
If the master device sends an acknowledge signal, the control-register address is incremented by 1. The slave device sends the data byte from the addressed register. To reduce program load time, the device supports address auto incrementation. The register address is incremented after each 8 data bits.
The read cycle ends when the master device does not generate an acknowledge signal after a data byte and generates a stop condition.