The regulator control loop relies on the ESR of the output capacitor to provide a zero to add sufficient phase margin to provide unconditional regulator stability. This condition requires the closed-loop gain to intersect the open-loop response in a region where the open-loop gain rolls off at 20dB/decade. This roll off makes sure that the phase is always less than 180° (phase margin greater than 0°) at unity gain. Thus, a minimum-maximum range for the ESR must be observed.

The upper limit of this ESR range is established by the fact that an ESR that is too high can result in the zero occurring too soon, causing the gain to roll off too slowly. This effect, in turn, allows a third pole to appear before unity gain and introduces enough phase shift to cause instability. This phase shift typically limits the maximum ESR to approximately 5Ω.

Conversely, the lower limit of the ESR range is tied to the fact that an ESR that is too low shifts the zero too far out, past unity gain, which allows the gain to roll off at 40dB/decade at unity gain, resulting in a phase shift of greater than 180°. Typically, this limits the minimum ESR to approximately 20mΩ to 30mΩ.

For specific ESR requirements, see the Section 5.7 section.