9.1.4 PCB Summary
- Minimize the parasitic inductance by keeping the power path components close together and keeping the area of the high-current loops small.
- The most important consideration when completing the layout is the close coupling of the GND connections of the CIN capacitor and the catch diode D1. These ground connections must be immediately adjacent, with multiple vias in parallel at the pad of the input capacitor connected to GND. Place CIN and D1 as close to the IC as possible.
- Next in importance is the location of the GND connection of the COUT capacitor, which should be near the GND connections of CIN and D1.
- There should be a continuous ground plane on the copper layer directly beneath the converter. This reduces parasitic inductance and EMI.
- The FB pin is a high impedance node — take care to make the FB trace short to avoid noise pickup and inaccurate regulation. Place the feedback resistors as close as possible to the IC, with the GND of R2 placed as close as possible to the GND of the IC. The VOUT trace to R1 should be routed away from the inductor and any other traces that are switching.
- High AC currents flow through the VIN, SW and VOUT traces, so they must be as short and wide as possible. However, making the traces wide increases radiated noise, so the layout designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor.
Place the remaining components as close as possible to the IC. See AN-2279 LMR12020 Evaluation Module for further considerations and the LMR12015/20 eval board as an example of a four-layer layout.