ZHCSLM0A May 2020 – January 2021 LMK5B12204
PRODUCTION DATA
The TDC input compares the phase of the R divider clock of the selected reference input and the DPLL feedback divider clock from VCO1. The TDC output generates a digital correction word corresponding to the phase error which is processed by the DPLL loop filter.
The DPLL TDC input frequency (fTDC) can operate up to 26 MHz and can be computed by Equation 3.