10.3 Termination and Use of Clock Drivers
When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance:
- Transmission line theory should be followed for good impedance matching to prevent reflections.
- Clock drivers should be presented with the proper loads.
- LVDS outputs are current drivers and require a closed current loop.
- HCSL drivers are switched current outputs and require a DC path to ground via 50 Ω termination.
- LVPECL outputs are open emitter and require a DC path to ground.
- Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level; in this case, the signal should normally be AC coupled.
It is possible to drive a non-LVPECL or non-LVDS receiver with a LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure the receiver is biased at the optimum DC voltage (common mode voltage).