ZHCSH72J september   2011  – may 2023 LMK00301

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VCC and VCCO Power Supplies
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Inputs
      2. 9.4.2 Clock Outputs
        1. 9.4.2.1 Reference Output
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Driving the Clock Inputs
        2. 10.2.1.2 Crystal Interface
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Termination and Use of Clock Drivers
          1. 10.2.2.1.1 Termination for DC Coupled Differential Operation
          2. 10.2.2.1.2 Termination for AC Coupled Differential Operation
          3. 10.2.2.1.3 Termination for Single-Ended Operation
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 Power Supply Sequencing
    2. 11.2 Current Consumption and Power Dissipation Calculations
      1. 11.2.1 Power Dissipation Example #1: Separate VCC and VCCO Supplies with Unused Outputs
      2. 11.2.2 Power Dissipation Example #2: Worst-Case Dissipation
    3. 11.3 Power Supply Bypassing
      1. 11.3.1 Power Supply Ripple Rejection
    4. 11.4 Thermal Management
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  15. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.4.1 Clock Inputs

The input clock can be selected from CLKin0/CLKin0*, CLKin1/CLKin1*, or OSCin. Clock input selection is controlled using the CLKin_SEL[1:0] inputs as shown in Table 9-1. See Driving the Clock Inputs for clock input requirements. When CLKin0 or CLKin1 is selected, the crystal circuit is powered down. When OSCin is selected, the crystal oscillator circuit starts up and the clock are distributed to all outputs. See Crystal Interface for more information. Alternatively, OSCin may be driven by a single-ended clock (up to 250 MHz) instead of a crystal.

Table 9-1 Input Selection
CLKin_SEL1CLKin_SEL0SELECTED INPUT
00CLKin0, CLKin0*
01CLKin1, CLKin1*
1XOSCin

Table 9-2 shows the output logic state versus input state when either CLKin0/CLKin0* or CLKin1/CLKin1* is selected. When OSCin is selected, the output state will be an inverted copy of the OSCin input state.

Table 9-2 CLKin Input vs Output States
STATE OF
SELECTED CLKin		STATE OF
ENABLED OUTPUTS
CLKinX and CLKinX*
inputs floating		Logic low
CLKinX and CLKinX*
inputs shorted together		Logic low
CLKin logic lowLogic low
CLKin logic highLogic high