ZHCSH72I
September 2011 – December 2017
LMK00301
PRODUCTION DATA.
1
特性
2
应用
3
说明
Device Images
功能框图
LVPECL 输出摆幅 (VOD) 与频率间的关系
4
修订历史记录
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Parameter Measurement Information
8.1
Differential Voltage Measurement Terminology
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.2.1
Functional Block Diagram
9.3
Feature Description
9.3.1
VCC and VCCO Power Supplies
9.3.2
Clock Inputs
9.3.3
Clock Outputs
9.3.3.1
Reference Output
10
Application and Implementation
10.1
Driving the Clock Inputs
10.2
Crystal Interface
10.3
Termination and Use of Clock Drivers
10.3.1
Termination for DC Coupled Differential Operation
10.3.2
Termination for AC Coupled Differential Operation
10.3.3
Termination for Single-Ended Operation
11
Power Supply Recommendations
11.1
Power Supply Sequencing
11.2
Current Consumption and Power Dissipation Calculations
11.2.1
Power Dissipation Example #1: Separate Vcc and Vcco Supplies with Unused Outputs
11.2.2
Power Dissipation Example #2: Worst-Case Dissipation
11.3
Power Supply Bypassing
11.3.1
Power Supply Ripple Rejection
11.4
Thermal Management
12
器件和文档支持
12.1
文档支持
12.1.1
相关文档
12.2
社区资源
12.3
商标
12.4
静电放电警告
12.5
Glossary
13
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RHS|48
MPQF159B
散热焊盘机械数据 (封装 | 引脚)
RHS|48
QFND509A
订购信息
zhcsh72i_oa
zhcsh72i_pm
1
特性
3:1 输入多路复用器
两个通用输入运行频率高达 3.1GHz,且支持 LVPECL、LVDS、CML、SSTL、HSTL、HCSL 或单端时钟
单个晶振输入支持 10 至 40 MHz 的晶振或单端时钟
共两组,每组均具有 5 路差动输出
LVPECL,LVDS,HCSL 或高阻抗 (Hi-Z)(每个组可选)
LMK03806 时钟源为 156.25MHz 时,LVPECL 附加抖动:
20fs RMS(10kHz 至 1MHz)
51fs RMS(12kHz 至 20MHz)
高 PSRR:-65/-76dBc (LVPECL/LVDS)@156.25MHz
具有同步使能驶入的 LVCMOS 输出
由引脚控制的配置
V
CC
内核电源:3.3V ± 5%
3 个独立的 V
CCO
输出电源:3.3V/2.5V ± 5%
工业温度范围:-40°C 至 +85°C