ZHCSDA5F June   2012  – February 2015 LMH6881

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
      1. 6.6.1 Single-Ended Input
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Digital Control of the Gain and Power-Down Pins
        1. 7.5.1.1 Parallel Interface
        2. 7.5.1.2 SPI-Compatible Serial Interface
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Characteristics
      2. 8.1.2 Output Characteristics
      3. 8.1.3 Interfacing to an ADC
        1. 8.1.3.1 ADC Noise Filter
        2. 8.1.3.2 AC Coupling to ADC
        3. 8.1.3.3 DC Coupling to ADC
      4. 8.1.4 Figure of Merit: Dynamic Range Figure
    2. 8.2 Typical Applications
      1. 8.2.1 LMH6881 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LMH6881 Used as Twisted-Pair Cable Driver
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Uncontrolled Impedance Traces
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档 
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Detailed Description

7.1 Overview

The LMH6881 has been designed to replace traditional, fixed-gain amplifiers, as well as variable-gain amplifiers, with an easy-to-use device which can be flexibly configured to many different gain settings while maintaining excellent performance over the entire gain range. Many systems can benefit from this programmable-gain, DC-capable, differential amplifier. Last-minute design changes can be implemented immediately, and external resistors are not required to set the gain.

The LMH6881 is a fully differential amplifier optimized for signal-path applications up to 1000 MHz. The LMH6881 has a 100-Ω input impedance and a low (less than 0.5 Ω) impedance output. The gain is digitally controlled over a 20-dB range from 26 dB to 6 dB. The LMH6881 is designed to replace fixed-gain differential amplifiers with a single, flexible-gain device. It has been designed to provide good noise figure and OIP3 over the entire gain range. This design feature is highlighted by the DRF of merit. Traditional variable gain amplifiers generally have the best OIP3 and NF performance at maximum gain only.

Gain control is enabled with a parallel or a serial-control interface, and as a result, the amplifier can also serve as a digitally controlled variable-gain amplifier (DVGA) for automatic gain-control applications. Figure 37 and Figure 38 show typical implementations of the amplifier.

7.2 Functional Block Diagram

LMH6881 FBD_01_SBAS662.gif

7.3 Feature Description

The LMH6881 has three functional stages, a low-noise amplifier, followed by a digital attenuator, and a low-distortion, low-impedance output amplifier. The amplifier has four signal-input pins, to accommodate both differential signals and single-ended signals. The amplifier has an OCM pin used to set the output common mode voltage. There is a gain of 2 on this pin so that 1.25 V applied on that pin will place the output common mode at 2.5 V.

LMH6881 30195801.gifFigure 37. Typical Implementation With a Differential Input Signal
LMH6881 30195894.gifFigure 38. Typical Implementation With a Single-Ended Input Signal

7.4 Device Functional Modes

The LMH6881 will support two modes of control for its gain: a parallel mode and a serial mode (SPI compatible). Parallel mode is fastest and requires the most board space for logic line routing. Serial mode is compatible with existing SPI-compatible systems. The device has gain settings covering a range of 20 dB. In parallel mode, only 2-dB steps are available. The serial interface should be used for finer gain control of 0.25 dB for a gain between 6 dB and 26 dB of voltage gain. If fixed gain is desired, the digital pins can be strapped to ground or VCC, as required.

The device also supports two modes of power down control to enable power savings when the amplifier is not being used: using the SD pin (when SPI pin = Logic 0) and the power-down register (when SPI pin = Logic 1).

7.5 Programming

7.5.1 Digital Control of the Gain and Power-Down Pins

The LMH6881 was designed to interface with 2.5-V to 5-V CMOS logic circuits. If operation with 5-V logic is required, care should be taken to avoid signal transients exceeding the supply voltage of the amplifier. Long, unterminated digital signal traces should be avoided. Signal voltages on the logic pins that exceed the device power supply voltage may trigger ESD protection circuits and cause unreliable operation. Some digital input-output pins have different functions depending on the digital control mode. Table 1 shows the mapping of the digital pins. These functions for each pin will be described in the sections Parallel Interface and SPI-Compatible Serial Interface.

Table 1. Pins With Dual Functions

Pin SPI = 0 SPI = 1
3 D1 SDI
4 D0 SDO(1)
15 D2 CLK
16 D3 CS (active low)
(1) Pin 4 requires external bias. See SPI-Compatible Serial Interface section for Details.

7.5.1.1 Parallel Interface

Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space dedicated to control lines. To place the LMH6881 into parallel mode the SPI pin (pin 5) is set to the logical zero state. Alternately the SPI pin can be connected directly to ground. The SPI pin has a weak internal resistor to ground. If left unconnected, the amplifier will operate in parallel mode.

In parallel mode the gain can be changed in 2-dB steps with a 4-bit gain control bus. The attenuator control pins are internally biased to logic high state with weak pull-up resistors, with the exception of D0 which is biased low due to the shared SDO function. If the control bus is left unconnected, the amplifier gain will be set to 6 dB. Table 2 shows the gain of the amplifier when controlled in parallel mode.

Table 2. Amplifier Gain for All Control Pin Combinations

CONTROL PINS LOGICAL LEVEL IN PARALLEL MODE
D3 D2 D1 D0 DECIMAL VALUE AMPLIFIER VOLTAGE GAIN [dB]
1 X 1 X 10 - 15 6
1 0 0 1 9 8
1 0 0 0 8 10
0 1 1 1 7 12
0 1 1 0 6 14
0 1 0 1 5 16
0 1 0 0 4 18
0 0 1 1 3 20
0 0 1 0 2 22
0 0 0 1 1 24
0 0 0 0 0 26

For fixed-gain applications the attenuator-control pins should be connected to the desired logic state instead of relying on the weak internal bias. Data from the gain-control pins directly drive the amplifier gain circuits. To minimize gain change glitches all gain pins should be driven with minimal skew. If gain-pin timing is uncertain, undesirable transients can be avoided by using the shutdown pin to disable the amplifier while the gain is changed. Gain glitches are most likely to occur when multiple bits change value for a small gain change, such as the gain change from 10 dB to 12 dB which requires changing all 4 gain-control pins.

A shutdown pin (SD == 0, amplifier on, SD == 1, amplifier off) is provided to reduce power consumption by disabling the highest power portions of the amplifier. The digital control circuit is not shut down and will preserve the last active gain setting during the disabled state. See the Typical Characteristics section for disable and enable timing information. The SD pin is functional in parallel mode only and disabled in serial mode.

LMH6881 30195817.gifFigure 39. Parallel Mode Connection

7.5.1.2 SPI-Compatible Serial Interface

The serial interface allows a great deal of flexibility in gain programming and reduced board complexity. The LMH6881 serial interface is a generic 4-wire synchronous interface that is compatible with SPI-type interfaces that are used on many microcontrollers and DSP controllers. Using only four wires, the SPI mode offers access to the 0.25-dB gain steps of the amplifier.

For systems where gain is changed only infrequently, or where only slower gain changes are required, serial mode is the best choice. To place the LMH6881 into serial mode the SPI pin (Pin 5) should be put into the logic high state. Alternatively the SPI pin can be connected directly to the 5-V supply bus. In this configuration the pins function as shown in Table 1. The SPI interface uses the following signals: clock input (CLK), serial data in (SDI), serial data out (SDO), and serial chip select (CS). The chip-select pin is active low meaning the device is selected when the pin is low.

The SD pin is inactive in the serial mode. This pin can be left disconnected for serial mode. The SPI interface has the ability to shut down the amplifier without using the SD pin.

The CLK pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the rising edge and to source the output data on the SDO pin on the falling edge. The user may disable clock and hold it in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled or disabled. The clock pulse-width minimum is equal to one setup plus one hold time, or 6 ns.

The CS pin is the chip-select pin. This pin is active low; the chip is selected in the logic low state. Each assertion starts a new register access - that is, the SDATA field protocol is required. The user is required to deassert this signal after the 16th clock. If the CS pin is deasserted before the 16th clock, no address or data write will occur. The rising edge captures the address just shifted in and, in the case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the de-asserted pulse, which is specified in the Specifications section.

The SDI pin is the input pin for the serial data. Each write cycle is 16-bits long.

The SDO pin is the data output pin. This output is normally at a high impedance state, and is driven only when CS is asserted. Upon CS assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges. The SDO pin is a current output and requires external bias resistor to develop the correct logic voltage. See Figure 41 for details on sizing the external bias resistor. Resistor values of 180 Ω to 400 Ω are recommended. The SDO pin can source 10 mA in the logic high state. With a bias resistor of 250 Ω the logic 1 voltage would be 2.5 V. In the logic 0 state, the SDO output is off and no current flows, so the bias resistor will pull the voltage to 0 V.

Each serial interface write access cycle is exactly 16 bits long as shown in Figure 40.

The external bias resistor means that in the high-impedance state the SDO pin impedance is equal to the external bias resistor value. If busing multiple SPI devices make sure that the SDO pins of the other devices can drive the bias resistor. The serial interface has four registers with address [0] to address [3]. Table 3 shows the content of each SPI register. Registers 0 and 1 are read only. Registers 2 and 3 are read/write and control the gain and power of the amplifier. Table 4 shows the data format of register 2 and Table 5 shows the data format of register 3.

Table 3. SPI Registers

Address Read/Write Name Description Default value [Hex]
0 R Revision ID Revision of the product 1 (first revision)
1 R Product ID Identification of the product 20
2 R/W Power down Power up/down of the amplifier 0
3 R/W Attenuation Attenuation control 50

Table 4. Register 2 Definition

7 6 5 4 3 2 1 0
Reserved OFF = 1,1: ON = 0,0 Reserved

Table 5. Register 3 Definition

7 6 5 4 3 2 1 0
Reserved 16dB 8dB 4dB 2dB 1dB 0.5dB 0.25dB
Gain [dB] = 26- (Register3 * 0.25); valid range is 0 to 80 in decimal.
LMH6881 30195812.gifFigure 40. Serial Interface Protocol (SPI Compatible)
LMH6881 30195814.gifFigure 41. Internal Operation of the SDO Pin