ZHCSIC9D April   2016  – June 2018 LMH1219

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Recommended SMBus Interface AC Timing Specifications
    7. 6.7 Serial Parallel Interface (SPI) AC Timing Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  4-Level Input Configuration Pins
      2. 7.3.2  Input Carrier Detect
      3. 7.3.3  -6 dB Splitter Mode Launch Amplitude for IN0
      4. 7.3.4  Continuous Time Linear Equalizer (CTLE)
        1. 7.3.4.1 Adaptive Cable Equalizer (IN0+)
        2. 7.3.4.2 Adaptive PCB Trace Equalizer (IN1±)
      5. 7.3.5  Input-Output Mux Selection
      6. 7.3.6  Clock and Data Recovery (CDR) Reclocker
      7. 7.3.7  Internal Eye Opening Monitor (EOM)
      8. 7.3.8  Output Function Control
      9. 7.3.9  Output Driver Amplitude and De-Emphasis Control
      10. 7.3.10 Status Indicators and Interrupts
        1. 7.3.10.1 LOCK_N (Lock Indicator)
        2. 7.3.10.2 CD_N (Carrier Detect)
        3. 7.3.10.3 INT_N (Interrupt)
      11. 7.3.11 Additional Programmability
        1. 7.3.11.1 Cable Length Indicator (CLI)
        2. 7.3.11.2 Digital MUTEREF
    4. 7.4 Device Functional Modes
      1. 7.4.1 System Management Bus (SMBus) Mode
        1. 7.4.1.1 SMBus Read and Write Transactions
          1. 7.4.1.1.1 SMBus Write Operation Format
          2. 7.4.1.1.2 SMBus Read Operation Format
      2. 7.4.2 Serial Peripheral Interface (SPI) Mode
        1. 7.4.2.1 SPI Read and Write Transactions
          1. 7.4.2.1.1 SPI Write Transaction Format
          2. 7.4.2.1.2 SPI Read Transaction Format
        2. 7.4.2.2 SPI Daisy Chain
    5. 7.5 LMH1219 Register Map
      1. 7.5.1 Share Register Page
      2. 7.5.2 CTLE/CDR Register Page
      3. 7.5.3 CableEQ/Drivers Register Page
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for SMPTE and 10 GbE Applications
      2. 8.1.2 Optimizing Time to Adapt and Lock
      3. 8.1.3 LMH1219 and LMH0324 Compatibility
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detail Design Procedure
      3. 8.2.3 Recommended VOD and DEM Register Settings
      4. 8.2.4 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.1 Share Register Page

Address Register Name Bit Field Default Type Description
0x00 Reserved 7:0 Reserved 0x00 R Reserved
0x01 Reserved 7:0 Reserved 0x40 R Reserved
0x02 Reserved 7:0 Reserved 0x02 RW Reserved
0x03 Reserved 7:0 Reserved 0x00 RW Reserved
0x04 Reserved 7:0 Reserved 0x01 RW Reserved
0x05 Reserved 7:0 Reserved 0x00 RW Reserved
0x06 Reserved 7:0 Reserved 0x00 RW Reserved
0x07 Reserved 7:0 Reserved 0x04 RW Reserved
0x08 Reserved 7:0 Reserved 0x11 RW Reserved
0x09 Reserved 7:0 Reserved 0x00 R Reserved
0xE2 Reset Share/Channel Regs 7:5 Reserved 0x10 R Reserved
4 reset_done R 0 = Internal state machine register initialization not done.
1 = Internal state machine register initialization done.
3:1 Reserved RW Reserved
0 reset_init RW 1 = Initialize internal state machine register settings. Refer to the LMH1219 Programming Guide for details.
0xF0 Device Revision 7:0 Version 0x02 R Device Revision
0xF1 Device ID 7:0 Device_ID 0x80 R For LMH1219, Device ID = 0x80
0xFF Register Communication Control 7:6 lock_output_ctrl 0x00 RW Controls the output on LOCK pin if Reg 0xFF[5:4] = 01'b
00 = Lock status from Reclocker
01 = CableEQ/Driver Reg 0x00[7] status output
10 = Logical OR of LOCK status from Reclocker and CableEQ/Driver Reg 0x00[7] status
11 = Logical AND of LOCK status from Reclocker and CableEQ/Driver Reg 0x00[7] status
5:4 los_int_bus_sel RW Controls the output on LOCK_N pin
00 = Default behavior (LOCK_N outputs lock status from reclocker)
01 = LOCK_N pin output status determined by Reg 0xFF[7:6]
10 = LOS of selected input (IN0 or IN1)
11 = Interrupts are output on LOCK_N pin, as determined by CTLE/CDR Page Reg 0x56[6:0]
3 Reserved RW Reserved
2 page_select_enable RW 0 = The shared registers are enabled.
1 = Enables communication access to the Register Page specified in Reg 0xFF[1:0].
1:0 page_select RW Enable communication access to a specific Register Page
00 = CTLE/CDR Register Page
01 = CableEQ/Drivers Register Page
Other values are invalid.