ZHCST41 September   2023 LMG3624

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 GaN Power FET Switching Capability
      2. 8.3.2 Turn-On Slew-Rate Control
      3. 8.3.3 Current-Sense Emulation
      4. 8.3.4 Input Control Pins (EN, IN)
      5. 8.3.5 AUX Supply Pin
        1. 8.3.5.1 AUX Power-On Reset
        2. 8.3.5.2 AUX Under-Voltage Lockout (UVLO)
      6. 8.3.6 Overcurrent Protection
      7. 8.3.7 Overtemperature Protection
      8. 8.3.8 Fault Reporting
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

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6.6 Switching Characteristics

1) Symbol definitions: ID = D to S current;  IS = S to D current; ICS(src) = current out of CS;  2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; –40°C ≤ TJ ≤ 125°C; 10 V ≤ VAUX ≤ 26 V; VEN = 5 V; VIN = 0 V; RRDRV = 0 Ω; RCS = 100 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER FET 
td(on)(Idrain) Drain current turn-on delay time From VIN > VIN,IT+ to ID > 37.5 mA, VBUS = 400 V, LHB current = 1.5 A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 68 ns
slew rate setting 1 40
slew rate setting 2 35
slew rate setting 3 (fastest) 34
td(on) Turn-on delay time From VIN > VIN,IT+ to VDS < 320 V, VBUS = 400 V, LHB current = 1.5 A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 91 ns
slew rate setting 1 50
slew rate setting 2 43
slew rate setting 3 (fastest) 37
tr(on) Turn-on rise time From VDS < 320 V to VDS < 80 V, VBUS = 400 V, LHB current = 1.5 A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 14.9 ns
slew rate setting 1 5.6
slew rate setting 2 3.8
slew rate setting 3 (fastest) 1.9
td(off) Turn-off delay time From VIN < VIN,IT– to VDS > 80 V, VBUS = 400 V, LHB current = 1.5 A, (independent of slew rate setting), see GaN Power FET Switching Parameters 43 ns
tf(off) Turn-off fall time From VDS > 80 V to VDS > 320 V, VBUS = 400 V, LHB current = 1.5 A, (independent of slew rate setting), see GaN Power FET Switching Parameters 12.5 ns
Turn-on slew rate From VDS < 250 V to VDS < 150 V, TJ = 25℃, VBUS = 400 V, LHB current = 1.5 A, at following slew rate settings, see GaN Power FET Switching Parameters
slew rate setting 0 (slowest) 20 V/ns
slew rate setting 1 50
slew rate setting 2 100
slew rate setting 3 (fastest) 150
CS
tr Rise time From ICS(src) > 0.1 × ICS(src)(final) to ICS(src) > 0.9 × ICS(src)(final), 0 V ≤ VCS ≤ 2 V, enabled into a 1.5-A load 35 ns
EN
EN Wake-up time From VEN > VIT+ to ID(ls) > 10 mA, VINL = 5 V 1 µs