ZHCST41 September   2023 LMG3624

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 GaN Power FET Switching Capability
      2. 8.3.2 Turn-On Slew-Rate Control
      3. 8.3.3 Current-Sense Emulation
      4. 8.3.4 Input Control Pins (EN, IN)
      5. 8.3.5 AUX Supply Pin
        1. 8.3.5.1 AUX Power-On Reset
        2. 8.3.5.2 AUX Under-Voltage Lockout (UVLO)
      6. 8.3.6 Overcurrent Protection
      7. 8.3.7 Overtemperature Protection
      8. 8.3.8 Fault Reporting
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.4.1.1 Solder-Joint Stress Relief

Large QFN packages can experience high solder-joint stress. Several best practices are recommended to provide solder-joint stress relief. First, the instructions for the NC1, NC2, and NC3 anchor pins found in Table 5-1 must be followed. Second, all the board solder pads must be non-solder-mask defined (NSMD) as shown in the land pattern example in the Mechanical, Packaging, and Orderable Infromation section. Finally, any board trace connected to an NSMD pad must be less than two thirds the width of the pad on the pad side where it is connected. The trace must maintain this two-thirds width limit for as long as it is not covered by solder mask. After the trace is under solder mask, there are no limits on the trace dimensions. All these recommendations are followed in the Layout Example section.