ZHCSIP2E April   2016  – October 2018 LMG3410R070 , LMG3411R070

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化方框图
      2.      高于 100V/ns 时的开关性能
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-on Delays
      2. 7.1.2 Turn-off Delays
      3. 7.1.3 Drain Slew Rate
      4. 7.1.4 Turn-on and Turn-off Energy
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Direct-Drive GaN Architecture
      2. 8.3.2 Internal Buck-Boost DC-DC Converter
      3. 8.3.3 Internal Auxiliary LDO
      4. 8.3.4 Fault Detection
        1. 8.3.4.1 Over-current Protection
        2. 8.3.4.2 Over-Temperature Protection and UVLO
      5. 8.3.5 Drive Strength Adjustment
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
      3. 9.2.3 Application Curves
    3. 9.3 Paralleling GaN Devices
    4. 9.4 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Using an Isolated Power Supply
    2. 10.2 Using a Bootstrap Diode
      1. 10.2.1 Diode Selection
      2. 10.2.2 Managing the Bootstrap Voltage
      3. 10.2.3 Reliable Bootstrap Start-up
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Loop Inductance
      2. 11.1.2 Signal Ground Connection
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Switch-Node Capacitance
      5. 11.1.5 Signal Integrity
      6. 11.1.6 High-Voltage Spacing
      7. 11.1.7 Thermal Recommendations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 Switching Characteristics

over operating free-air temperature range, 9.5 V < VDD < 18 V, VNEG = -14 V, VBUS = 400 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GaN FET
dv/dt Turn-on Drain Slew Rate RDRV = 15 kΩ 100 V/ns
RDRV = 40 kΩ 50
RDRV = 100 kΩ 25
Δdv/dt Slew Rate Variation turn on, IL = 5 A, RDRV = 40 kΩ 25 %
dv/dt Edge Rate Immunity Drain dv/dt, device remains off inductor-fed, max di/dt = 10 A/ns 150 V/ns
STARTUP
tSTART Startup Time, VIN rising above UVLO Time until gate responds to IN CNEG = 2.2 µF, CLDO = 1 µF 1 ms
DRIVER
tpd,on Propagation delay, turn on IN rising to IDS > 1 A, VDS = 400 V RDRV = 40 kΩ, VNEG = -14 V 20 ns
tdelay,on Turn on delay time IDS > 1 A to VDS < 320 V, RDRV = 40 kΩ 12 ns
tVDS,ft VDS fall time VDS = 320 V to VDS = 80 V, ID = 5 A 4.2 ns
tpd,off Propagation delay, turn off IN falling to VDS > 10 V; ID = 5 A 36 ns
tdelay,off Turn off delay time VDS = 10 V to VDS = 80 V, ID = 5 A 10 ns
tVDS,rt VDS rise time VDS = 80 V to VDS = 320 V, ID = 5 A 15 ns
FAULT
tcurr Current Fault Delay IDS > ITH to FAULT low 50 ns
tblank Current Fault Blanking Time VIN>VIH to end of blanking,  RDRV=15kΩ 55 ns
treset Fault reset time IN held low 250 350 500 µs