Figure 7-10 presents a typical layout of LMG1020-Q1 with a 0402 decoupling capacitor C1, which is placed as close as possible to LMG1020-Q1. The ground return at GaN FET Kelvin source immediately flows through a via to the closest inner layer, and overlaps with the top layer traces.

Figure 7-11 presents a layout of LMG1020-Q1 with a 0.1µF feed-through capacitor (C1) and a larger 1μF capacitor (C3) for decoupling. In this design, the feed-through capacitor C1 is placed in a shunt-through manner for lower noise decoupling, and C3 is placed next to C1. 0201 resistors are used at the output of LMG1020-Q1, which brings lower parasitic inductance than 0402 package.

Figure 7-10 Typical LMG1020-Q1 Layout With Ball-Grid GaN FET And 0402 Decoupling Capacitor

Figure 7-11 Typical Layout Of LMG1020-Q1 And A Feed-Through Decoupling Capacitor With A Capacitor Load