ZHCSJE7A March   2019  – September 2019 LM76202-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      24V 条件下的 ISO16750-2 负载突降脉冲 5b 性能
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1      Absolute Maximum Ratings
    2. 6.2      ESD Ratings
    3. 6.3      Recommended Operating Conditions
    4. Table 1. Thermal Information
    5. 6.4      Electrical Characteristics
    6. 6.5      Timing Requirements
    7. 6.6      Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Overvoltage Protection (OVP)
      3. 8.3.3 Reverse Battery Protection
      4. 8.3.4 Hot Plug-In and In-Rush Current Control
      5. 8.3.5 Overload and Short Circuit Protection
        1. 8.3.5.1 Overload Protection
          1. 8.3.5.1.1 Active Current Limiting
          2. 8.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN
        2. 8.3.5.2 Short Circuit Protection
          1. 8.3.5.2.1 Start-Up With Short-Circuit On Output
        3. 8.3.5.3 FAULT Response
          1. 8.3.5.3.1 Look Ahead Overload Current Fault Indicator
        4. 8.3.5.4 Current Monitoring
        5. 8.3.5.5 IN, OUT, RTN and GND Pins
        6. 8.3.5.6 Thermal Shutdown
        7. 8.3.5.7 Low Current Shutdown Control (SHDN)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step by Step Design Procedure
        2. 9.2.2.2 Setting Undervoltage Lockout and Overvoltage Set Point for Operating Voltage Range
        3. 9.2.2.3 Programming the Current-Limit Threshold—R(ILIM) Selection
        4. 9.2.2.4 Programming Current Monitoring Resistor—RIMON
        5. 9.2.2.5 Limiting the Inrush Current
          1. 9.2.2.5.1 Selection of Input TVS for Transient Protection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PWP|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.5.3 FAULT Response

The FLT open-drain output asserts (active low) under following conditions:

  • Fault events such as undervoltage, overvoltage, overload, reverse current and thermal shutdown conditions
  • When the device enters low current shutdown mode when SHDN is pulled low
  • During start-up when the internal FET GATE is not fully enhanced (for example: VOUT has not reached VIN).

The FLT output does not assert in the event of reverse voltage on Input.

The device is designed to eliminate false reporting by using an internal "de-glitch" circuit for fault conditions without the need for an external circuitry.

The FLT signal can also be used as Power Good indicator to the downstream loads like DC-DC converters. An internal Power Good (PGOOD) signal is OR'd with the fault logic. During start-up, when the device is operating in dVdT mode, PGOOD and FLT remains low and is de-asserted after the dVdT mode is completed and the internal FET is fully enhanced and VOUT has reached VIN. The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy load is applied by the downstream converters. Rising deglitch delay is determined by tPGOOD(degl) = Maximum {(900 + 20 × C(dVdT)), tPGOODR}, where C(dVdT) is in nF and tPGOOD(degl) is in µs. FLT can be left open or connected to RTN when not used. V(IN) falling below V(PORF) resets FLT.