7.3.1 Power Amplifier Synchronization (Tx1)

The TX1/TORCH/GPIO1 pin has a triple function. With configuration register 1 bit [7] = 0 (default) TX1/TORCH/GPIO1 is a power amplifier synchronization input (TX1 mode). This mode is designed to reduce the flash LED current when TX1 is driven high (active high polarity) or driven low (active low polarity). When the LM3560 is engaged in a flash event and TX1/TORCH is driven high, the active current sources (LED1 and/or LED2) are forced into torch mode at the programmed torch current setting. If TX1 is then pulled low before the flash pulse terminates, the LED current returns to the previous flash current level. At the end of the flash timeout, whether the TX1/TORCH pin is high or low, the LED current turns off.

The polarity of TX1 can be changed from active high to active low by writing a 0 to bit [5] of Configuration Register 1. With this bit set to 0 the LM3560 is forced into torch mode when TX1/TORCH is pulled low. Figure 21 details the functionality of the TX1 Interrupt.

7.3.1.1 TX1 Shutdown

TX1 also has the capability to force shutdown. Bit [4] of configuration register 2 set to a 1, changes TX1 from a force torch when active to a force shutdown when active. For example, if TX1/TORCH/GPIO1 is configured for TX1 mode with active high polarity, and bit[4] of configuration register 2 is set to 1, then when TX1 is driven high, the active current sources (LED1 and/or LED2) is forced into shutdown. Once the active current sources are forced into shutdown by activating TX1, the current sources can only be re-enabled into flash mode if TX1 is pulled low and the flags register is read back. If only the flags register is read back and TX1 is kept high the device is re-enabled into torch mode and not shutdown. This occurs because the TX1 shutdown feature is an edge-triggered event. With active high polarity the TX1 shutdown requires a rising edge at TX1 in order to force the current source into shutdown. Once shut down, it takes a read back of the flags register and another rising edge at TX1 to force shutdown again. Figure 34 details the different responses of the TX1 shutdown mode.

Figure 21. TX1 or TX2 Interrupt (Force Torch) Response

7.3.2 Independent LED Control

Bits [4:3] of the eenable register provide for independent turnon and turnoff of the LED1 or LED2 current sources. Once enabled, the LED current is adjusted by writing to the torch brightness or flash brightness registers depending on whether flash or torch mode is selected. Both the torch brightness and the flash brightness registers provide for independent current programming for the LED currents in either LED1 or LED2. (See Torch Brightness Register Descriptions (Address 0xA0) and Flash Brightness Register (Address 0xB0).)

7.3.3 Hardware Torch

With configuration register 1 Bit [7] = 1, TX1/TORCH/GPIO1 is configured as a hardware torch mode enable. In this mode, a high at TX1/TORCH turns on the LED current at the programmed torch current setting. The STROBE input and I²C-enabled flash takes precedence over torch mode. In hardware torch mode, both LED1 and LED2 current sources turn off after a flash event and configuration register 1 Bit [7] is reset to 0. In this situation, to re-enter torch mode via hardware torch, the hardware torch enable bit (configuration register 1 Bit [7]) must be reset to 1. Figure 22 details the functionality of hardware torch mode.

Figure 22. Hardware Torch Mode

7.3.4 Fault Protections

7.3.4.4 Indicator LED/Thermistor (LED1/NTC)

The LEDI/NTC pin serves a dual function: either as a programmable LED message indicator driver or as a comparator input for negative temperature coefficient (NTC) thermistors.

7.3.4.4.1 Message Indicator Current Source (LEDI/NTC)

LEDI/NTC is configured as a message indicator current source by setting configuration register 1 bit [4] = (0) default. The indicator current source is enabled/disabled via the enable register bit [6] = (1). Bit [7] of the enable register enables the message Indicator in blink mode. If the message indicator is set for blinking mode, the pattern programmed into the indicator register, and indicator blinking register is output on the Indicator current source.

The indicator blinking register controls the following (see Table 6):

1. Number of blank periods (BLANK #). This has 16 settings. t_BLANK = t_ACTIVE × BLANK# , where t_ACTIVE = t_PERIOD × PERIOD#
2. Pulse width (t_PULSE) has 16 settings between 0 and 480 ms in steps of 32 ms. The pulse width is the duration that the indicator current is at its programmed set point at the end of the ramp-up time.

The indicator register controls the following (see Table 5):

1. Indicator current level (I_IND). There are 8 indicator current levels from 2.25 mA to 18 mA in steps of 2.25 mA.
2. Number of periods (PERIOD #). This has 8 steps. A period (t_PERIOD) is found by
   t_PERIOD = t_R + t_F + 2 x t_PULSE. (see Figure 23 for indicator timing).
3. Ramp times (t_R or t_F) for turnon and turnoff of the indicator current source. Four programmable times of 78 ms, 156 ms, 312 ms, and 624 ms are available. The ramp times apply for both ramp-up and ramp-down and are not independently changeable.

Figure 23. Message Indicator Timing Diagram

7.3.4.4.1.1 Message Indicator Example 1 (Single Pulse With Dead Time):

As an example, to set up the message indicator for a 312-ms ramp-up and ramp-down, 192-ms pulse width, and 1 pulse followed by a 5-s delay. The indicator settings is as follows. t_R = t_F = 312 ms, t_WIDTH = 192 ms (t_PERIOD = 312 ms × 2 + 192 ms × 2 = 1016 ms). BLANK# setting is: 5s/1016 ms × 1 (PERIOD# = 1). Giving a BLANK# setting of 5. The resulting waveform appears as:

Figure 24. Message Indicator Example 1

7.3.4.4.1.2 Message Indicator Example 2 (Multiple Pulses With Dead Time):

Another example has the same t_R, t_F, t_PULSE, and t_BLANK times as before, but this time the PERIOD# is set to 3. Now the t_ACTIVE time is t_PERIOD × 3 = 1016 ms × 3 = 3048 ms. This results in a blank time of t_BLANK = t_ACTIVE × BLANK# = 3.048 s × 5 = 15.24 s

Figure 25. Message Indicator Example 2

7.3.4.4.2 Updating The Message Indicator

The best way to update the message indicator is to disable the message indicator output via the enable register bit [6], then write the new sequence to the indicator register and/or indicator blinking register, and then re-enable the message indicator. Updating the indicator registers while it is active can lead to long delays between pattern changes. This is especially true if the PERIOD#, or BLANK# setting is changed from a high setting to a lower setting.

7.3.5 Input Voltage Monitor

The LM3560 has an internal comparator at IN which monitors the input voltage and can force the LED current into torch mode or into shutdown if V_IN falls below the programmable V_IN monitor threshold. Bit 0 in the V_IN monitor register enables or disables this feature. When enabled, Bits [2:1] program the 4 adjustable thresholds of 2.9 V, 3 V, 3.1 V, and 3.2 V. Bit 3 in configuration register 2 selects whether a V_IN monitor event forces torch mode or forces LED1 and/or LED2 into shutdown. See Table 11 for additional information. When the input voltage monitor is active, and V_IN falls below the programmed V_IN monitor threshold, the LEDs turns off or is forced into the torch current setting. To reset the LED current to its previous level, two things must occur. First, V_IN must go above the V_IN monitor threshold, and the flags register must be read back. See Figure 26 for the V_IN monitor timing waveform.

To avoid noise from falsely triggering the V_IN monitor, this mode incorporates a 250 µs de-glitch timer. With the V_IN monitor active, V_IN must go below the V_IN monitor threshold (V_{IN_TH}), and remain below it, for 250 µs before the LEDs are forced into torch mode (or shutdown) and the V_IN monitor flag is written.

Figure 26. V_IN Monitor Waveform

1. For the V_IN flash monitor test, when the 2-A flash starts up the voltage at IN begins to drop via the rising input current ramp and the source resistance RS As soon as the input voltage crosses the programmed V_IN flash monitor threshold the flash current ramp is stopped, and the LM3560 flashes at the reduced current

2. For the V_IN monitor test, with a 2-A flash current the voltage at IN is V_BATT – I_BATT × R_S. When Q1 turns on the added load causes V_IN to drop by the additional current (V_IN / RL) which flows through R_S. When V_IN drops the programmed VIN monitor threshold is crossed, and the flash current pulse steps to the programmed torch current level causing V_IN to step up.

Figure 27. V_IN Monitor/V_IN Flash Monitor Test Circuit

7.3.6 Last Flash Register

Once the V_IN flash monitor is tripped, the flash code that corresponded to the LED current at which the flash current ramp was halted is written to the last flash register. The last flash register is a read-only register and has the lower 4 bits available to latch the code for LED1 and the upper 4 bits to latch the code for LED2.

For example, suppose that the LM3560 is set up for a single LED with a target flash current of 1250 mA and the V_IN flash monitor is enabled with the V_IN flash monitor threshold set to 3 V (V_IN monitor register bits [5:4] = 0, 1). When the STROBE input is brought high, the LED current begins ramping up through the torch and flash current codes at 32 µs/code. As the input current increases, the input voltage at the IN pin of the LM3560 device begins to fall due to the source impedance of the battery. By the time the LED current has reached 1000 mA (code 0x77 or 500 mA per current source), V_IN falls below 3 V. The V_IN flash monitor then stops the flash current ramp, and the LM3560 continues to proceed with the flash pulse, but at 1000 mA instead of 1250 mA. Figure 28 details this sequence.

Figure 28. V_IN Flash Monitor Example

7.3.7 LED Voltage Monitor

The LM3560 includes a 4-bit ADC which monitors the LED forward voltage (V_LED) and stores the digitized value in bits [3:0] of the V_LED monitor register. The highest voltage of V_LED1 or V_LED2 is automatically sensed and that becomes the sample point for the ADC. Bit 5, the ADC shutdown bit, enables/disables the ADC with the default state set to enable (bit [5] = 0).

7.3.8 ADC Delay

The ADC delay register provides for a programmable delay from 250 µs to 8 ms in steps of 250 µs. This delay is the delay from when the EOC bit goes low to when the V_LED monitor samples the LED voltage. In automatic mode the EOC bit goes low when the flash LED current hits its target. In Manual mode the EOC bit goes low at the end of a read back of the V_LED monitor register (or when the manual mode bit (bit 4) is re-written with a 1).

Figure 29. V_LED Monitor Automatic Mode

Figure 30. V_LED Monitor Manual Mode

7.3.9 Flags Register and Fault Indicators

Eight fault flags are available in the LM3560. These include a flash timeout, a thermal shutdown, an LED failure flag (LED shorted or output going OVP indicating LED open), an LED thermal flag (NTC threshold tripping), a V_IN monitor flag, and a V_IN flash monitor flag. Additionally, two LED interrupt flag bits (TX1 interrupt and TX2 interrupt) are set when the corresponding interrupt is activated. Reading back a 1 indicates the flagged event has happened. A read of the flags register resets these bits.

7.4.1 Start-Up (Enabling the Device)

Turnon of the LM3560 is done through bits [1:0] of the enable register. These bits enable the device in torch mode, flash mode, or privacy Indicate mode. Additionally, bit 6 of the enable register enables the message indicator at the LEDI/NTC pin. On start-up, when V_OUT is less than V_IN, the internal synchronous PFET turns on as a current source and delivers 350 mA to the output capacitor. During this time both current sources (LED1, and LED2) are off. When the voltage across the output capacitor reaches 2.2 V the current sources can turn on. At turnon the current sources step through each FLASH and TORCH level until their target LED current is reached (32 µs/step). This gives the device a controlled turnon and limits inrush current from the V_IN supply.

7.4.2 Pass Mode

On turnon, when the output voltage charges up to V_IN – 150 mV, the LM3560 operates in either pass mode or boost mode. If the voltage difference between V_OUT and V_LED is less then 300 mV, the device operates in boost mode. If the difference between V_OUT and V_LED is greater then 300 mV, the device operates in pass mode. In pass mode the boost converter stops switching and the synchronous PFET turns fully on bringing V_OUT up to V_IN – I_IN × R_PMOS where R_PMOS = 80 mΩ. In pass mode the inductor current is not limited by the peak current limit. In this situation the output current must be limited to 3 A.

7.4.3 Flash Mode

In flash mode the LED current sources (LED1 and LED2) each provide 16 different current levels from typically 62.5 mA (total) to 2 A (total) in steps of 62.5 mA. The flash currents are adjusted via the flash brightness register. Flash mode is activated by writing a (1, 1) to bits [1:0] of the enable register or by enabling the hardware flash input (STROBE) via bit [2] of Configuration Register 1, and then pulling the STROBE pin high (high polarity). Once the flash sequence is activated the active current sources (LED1 and/or LED2) ramps up to their programmed flash current level by stepping through all torch and flash levels (32 µs/step) until the programmed current is reached.

Bit [5] of the enable register (STROBE level/edge bit) determines how the flash pulse terminates after STROBE goes high. With the level/edge bit = 1, the flash current only terminates when it reaches the end of the flash timeout period. With the level/edge bit = 0, flash mode can be terminated by pulling STROBE low, programming bits [1:0] of the enable register with (0,0), or by allowing the flash timeout period to elapse. If the level/edge bit = 0 and STROBE is toggled before the end of the flash timeout period, the timeout period resets. Figure 31 and Figure 32 detail the flash pulse termination for the different level/edge bit settings.

Figure 31. LED Current for Strobe (Level Triggered, Enable Register Bit 5 = 0)

Figure 32. LED Current for Strobe (Edge Triggered, Enable Register Bit 5 = 1)

After the flash pulse terminates, either by a flash timeout, pulling STROBE low, or disabling it via the I²C-compatible interface, LED1 and LED2 turn completely off. This happens even when torch is enabled via the I²C-compatible interface and the flash pulse is turned on by toggling STROBE. After a flash event ends, bits [1:0] of the enable register are automatically reset with (0, 0). The exception occurs when the privacy terminate bit is low (bit [3]) in the privacy register. In this case, the specific current source that is enabled for privacy mode turns back on after the flash pulse.

7.4.4 Torch Mode

In torch mode the current sources LED1 and LED2 each provide 8 different current levels (Torch Brightness Register Descriptions (Address 0xA0)). Torch mode is activated by setting enable register bits [1:0] to (1, 0). Once torch mode is enabled, the current sources ramps up to the programmed torch current level by stepping through all of the torch currents at (32 µs/step) until the programmed torch current level is reached.

7.4.5 Privacy Indicator Mode

The current sources (LED1 and/or LED2) can also be used as a privacy indicator before and after flash mode. Privacy indicate mode is enabled by setting the enable register bit [1:0] to (0, 1). Privacy mode is configured via the privacy register. This allows the selection of which current source to use as the privacy indicator (either LED1, LED2, or both), whether or not the privacy indicate mode turns off at the end of the flash pulse, the 3 selectable privacy blink periods (t_BLINK), and the 8 duty cycle settings for the privacy indicator average current.

The intensity of the LEDs in privacy indicate mode is set by PWM controlling either the lowest torch current level (31.25 mA per current source) or the highest torch current level (250 mA per current source). Bit [2] in the enable register selects between these two levels. Bits [2:0] in the privacy register select the 8 different duty cycles of 10%, 20%, 30%, 40%, 50%, 60%, 70%, and 80%. This enables privacy mode to have a PWM-controlled torch current with a wide number of values (see Table 1 ). The privacy blink options (t_BLINK) are set via bit [7:6] of the privacy register. Selectable options are 128 ms, 256 ms, 512 ms, or always on. The blink pulse period is set to 2 × t_BLINK. Figure 33 details the timing for the privacy indicate mode timing on ILED1 or ILED2.

Figure 33. Privacy Indicate Timing

7.4.6 GPIO1 Mode

With bit [0] of the GPIO register set to 1, the TX1/TORCH/GPIO1 pin is configured as a logic I/O. In this mode the TX1/TORCH/GPIO1 pin is readable and writable as a logic input/output via bits [2:1] of the GPIO register (see GPIO Register (Address 0x20) for programming the GPIO1 output).

7.4.7 TX2/INT/GPIO2

The TX2/INT/GPIO2 pin has a triple function. In TX2 mode (default) the TX2/INT/GPIO2 pin is an active high flash interrupt. With GPIO register bit [3] = 1 the TX2/INT/GPIO2 pin is configured as general purpose logic I/O. With GPIO register bit [6] = 1, and with the TX2/INT/GPIO2 pin configured as a GPIO2 output, the TX2/INT/GPIO2 pin is an interrupt output.

7.4.8 TX2 Mode

In TX2 mode, when configuration register 1, bit [6] = 0, TX2 is an active low flash interrupt. Under this condition when the LM3560 is engaged in a flash event and TX2 is pulled low, the active current source (LED1 and/or LED2) are forced into torch mode. In TX2 mode with configuration register 1, bit [6] = 1, TX2 is configured for active high polarity. Under this condition, when the LM3560 is engaged in a flash event and TX2 is driven high, the active current source (LED1 and/or LED2) are forced into torch mode. During a TX2 interrupt event, if the TX2 input is disengaged, the LED current returns to the previous flash current level. Figure 21 details the functionality of the TX2 interrupt.

7.4.8.1 TX2 Shutdown

TX2 also has the capability to force shutdown. When bit [0] of configuration register 2 is set to a 1, TX2 forces shutdown when active. For example, if TX2 is configured for TX2 mode with active high polarity, and bit [0] of Configuration Register 2 is set to 1 then when TX2 is driven high, the active current sources (LED1 and/or LED2) is forced into shutdown. Once the active current sources are forced into shutdown by activating TX2, the current sources can only be re-enabled in flash mode if TX2 is pulled low and the flags register is read back. If only the flags register is read back and TX2 is kept high, the device is re-enabled into torch mode and not shut down. This occurs because the TX2 shutdown feature is an edge-triggered event. With active high polarity the TX2 shutdown requires a rising edge at TX2 in order to force the current sources into shutdown. Once shut down, it takes a read back of the flags register and another rising edge at TX2 to force shutdown again. Figure 34 details TX2 shutdown mode.

Figure 34. TX1 or TX2 (Force Shutdown) Response

7.4.9 GPIO2 Mode

With bit [3] of the GPIO fegister set to 1, the TX2/INT/GPIO2 pin is configured as a logic I/O. In this mode the TX2/INT/GPIO2 pin is readable and writable as a logic input/output via bits [5:4] of the GPIO register. See Table 8 for programming the GPIO2 output.

7.4.10 Interrupt Output (INT Mode)

The TX2/INT/GPIO2 pin can be reconfigured as an active low interrupt output by setting bit [6] in the GPIO register to 1 and configuring TX2/INT/GPIO2 as a GPIO2 output (bits [4:3] of GPIO register = 11). In this mode, TX2/INT/GPIO2 pulls low when any of these conditions exist:

1. The LM3560 is configured for NTC mode (configuration register 1 bit [4] = 1), and the voltage at LEDI/NTC has fallen below V_TRIP (1 V typical).
2. The LM3560 is configured for V_IN monitor mode (V_IN monitor register bit [0] = 1), and V_IN falls below the programmed V_IN monitor threshold.
3. The LM3560 is configured for V_IN flash monitor mode (V_IN monitor register bit [3] = 1), and V_IN falls below the programmed V_IN flash monitor threshold.

Once INT is pulled low due to any of the above conditions having been met, INT only goes high again if any of the conditions are no longer true and the flags register is read.

Figure 35. TX2 as an Interrupt Output (During an NTC Event)

7.4.11 NTC Mode

Writing a (1) to configuration register 1 bit [4] configures the LEDI/NTC pin for NTC mode. In this mode the indicator current source is disabled, and LEDI/NTC becomes the positive input to the an internal comparator. NTC mode operates as a LED current interrupt that is triggered when the voltage at LEDI/NTC goes below 1 V.

Two actions can be taken when the NTC comparator is tripped. With configuration register 2 bit [1] set to 0 the NTC interrupt forces the LED current from flash mode into torch mode. with configuration register 2 bit [1] set to 1, the NTC interrupt forces the LED current into shutdown.

Whether in NTC force torch or NTC shutdown, in order to re-enter flash mode after an NTC event, two things must occur. First, the NTC input must be above the 1-V threshold. Secondly, the flags register must be read.

To avoid noise from falsely triggering the NTC comparator, this mode incorporates a 250 µs de-glitch timer. With NTC mode active, V_LEDI/NTC must go below the trip point (V_TRIP) and remain below it for 250 µs before the LEDs are forced into torch mode (or shutdown) and the NTC flag is written.

7.4.12 Alternate External Torch (AET) Mode

With configuration register 2 bit [2] set to 1, the LM3560 is configured for AET mode, and the operation of TX1/TORCH becomes dependent on its occurrence relative to the STROBE input. In this mode, if TX1/TORCH goes high first, then STROBE goes high, the LEDs are forced into torch mode with no timeout. In this mode, if TX1/TORCH goes high after STROBE has gone high, then the TX1/TORCH pin operates as a normal LED current interrupt (TX1), and the LEDs turn off at the end of the timeout duration (see Figure 36).

Figure 36. AET Mode Timing

7.4.13 Automatic Conversion Mode

With the ADC enabled, a conversion is performed each time a flash pulse is started. When a flash pulse is started bit [6] of the V_LED monitor register end-of-conversion (EOC) bit is automatically written with a 0. At the end of the conversion, bit [6] goes high signaling that the V_LED data is valid. A read back of the V_LED monitor register clears the EOC bit. Figure 26 shows the V_LED monitor automatic conversion.

7.4.14 Manual Conversion Mode

When this bit is set high the EOC bit (bit [6]) goes low, and a conversion is performed. When the conversion is complete, the EOC bit goes high again. Subsequent conversions are performed in manual mode by reading back the V_LED monitor register, which resets the EOC bit and starts another conversion (see Figure 30).

7.5.1 START and STOP Conditions

The LM3560 is controlled via an I²C-compatible interface. START and STOP conditions classify the beginning and end of the I²C session. A START condition is defined as SDA transitioning from HIGH-to-LOW while SCL is HIGH. A STOP condition is defined as SDA transitioning from LOW-to-HIGH while SCL is HIGH. The I²C master always generates the START and STOP conditions.

Figure 37. START and STOP Sequences

The I²C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I²C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 38 shows the SDA and SCL signal timing for the I²C-compatible bus. See Electrical Characteristics for timing values.

Figure 38. I²C-Compatible Timing

7.5.2 I²C-Compatible Chip Address

The device address for the LM3560 is 1010011 (0xA7 for read and 0xA6 for write). After the START condition, the I²C master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data is written. The third byte contains the data for the selected register.

Figure 39. Device Address

7.5.3 Transferring Data

Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is generated by the master. The master releases SDA (HIGH) during the 9th clock pulse (write mode). The LM3560 pulls down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte has been received.

Table 2. LM3560 Internal Registers

7.6.1 Enable Register (Address 0x10)

Bits [1:0] of the enable register controls the on/off state of torch mode, flash mode, and privacy indicate mode. Bit 2 selects the peak current setting for privacy indicate mode (maximum or minimum torch current). Bits [4:3] turn on/off the main current sources (LED1 and LED2). Bit [5] sets the level or edge control for the STROBE input. Bits 7 and 6 control the Indicator current source (see Table 3).

7.6.2 Privacy Register (Address 0x11)

The privacy register contains the bits that control which current source is used for the privacy indicator (LED1 or LED2 or both), whether the privacy indicator turns off or remains on after the flash pulse terminates, and the duty cycle settings (between 10% and 80%) for setting the average privacy LED current (see Table 4 ).

7.6.3 Indicator Register (Address 0x12)

The Indicator register contains the bits which control the following:

1. Indicator current level
2. Pulse width
3. Ramp times for turnon and turnoff of the indicator current source (see Figure 40 for the message indicator timing diagram).

7.6.4 Indicator Blinking Register (Address 0x13)

The indicator blinking register contains the bits which control the following:

1. Number of periods (t_PERIOD = t_R + t_F + 2 × t_PULSE )
2. Active Time (t_ACTIVE = t_PERIOD × PERIOD# )
3. Blank Time (t_BLANK = t_ACTIVE × BLANK#)
   • (see Figure 40)

Figure 40. Message Indicator Timing Diagram

7.6.5 Privacy PWM Period Register (Address 0x14)

The privacy PWM register contains the bits to control the PWM period for the privacy indicate mode (see Table 7).

7.6.6 GPIO Register (Address 0x20)

The GPIO register contains the control bits which change the state of the TX1/TORCH/GPIO1 pin and the TX2/INT/GPIO2 pins to general purpose I/Os (GPIOs). Additionally, bit 6 of this register contains the interrupt configuration bit. Table 8 describes the bit description and functionality of the GPIO register. To configure the TX1 or TX2 pins as GPIO outputs an initial double write is required to register 0x20. For example, to configure TX2 to output a logic high, an initial write of 0xB8 would need to occur twice, to force GPIO2 low. Subsequent writes to GPIO2 after the initial set-up, only requires a single write. To read back the GPIO inputs, a write then a read of register 0x20 must occur each time the data is read. For example, if GPIO2 is set up as a GPIO input and the GPIO2 input has then changed state, first a write to 0x20 must occur, then the following read back of register 0x20 shows the updated data. When configuring TX2 as an interrupt output, the TX2/GPIO2/INT pin must first be configured as a GPIO output (double write). For example, to configure TX2/GPIO2/INT for INT mode a write of 0xF8 to register 0x20 must be done twice.

7.6.7 LED Forward Voltage ADC (V_LED Monitor Register, Address 0x30)

The V_LED monitor register controls the internal 4 bit analog to digital converter. Bits [3:0] of this register contain the 4-bit data of the LED voltage. This data is the digitized voltage of the highest of either V_LED1 to GND or V_LED2 to GND. Bit [4] is the manual mode enable which provides for a manual conversion of the ADC. In manual mode the automatic conversion is still performed. In automatic conversion mode a conversion is performed each time a flash pulse is initiated. Bit [5] is the ADC shutdown bit. Bit [6] signals the end of conversion. This is a read-only bit that goes high when a conversion is complete and data is ready. A read of the V_LED monitor register clears the end-of-conversion bit (see Table 9).

7.6.8 ADC Delay Register (Address 0x31)

The ADC delay register programs the delay from when the EOC bit goes low to when a conversion is initiated. This delay applies to both manual mode and automatic mode. Bit 5 is the no-delay bit and can set the delay to effectively 0.

7.6.9 V_IN Monitor Register (Address 0x80)

The V_IN monitor register controls the enable bit for the V_IN monitor, the threshold select for the V_IN monitor, the enable bit for the V_IN flash monitor, and the threshold select for the V_IN flash monitor (see Table 11).

7.6.10 Last Flash Register (Address 0x81)

The last flash register is a read-only register, which is loaded with the flash code corresponding to the flash level that the LM3560 device was at if any of the following events happen:

1. Voltage at LEDI/NTC falling below V_TRIP with the device in NTC mode (configuration register 1 bit [4] = 1);
2. Input voltage falling below the programmed V_IN monitor threshold with device in V_IN monitor mode (V_IN monitor register bit [0] = 1); or
3. Input voltage falling below the programmed V_IN flash monitor threshold with the device in V_IN flash monitor mode (V_IN monitor register bit [3] = 1).

The last flash register is updated at the same time that the corresponding flag bit is written to the flags register. This results in a delay of 250 µs from when V_LEDI/NTC (NTC mode) crosses V_TRIP, or V_IN (V_IN monitor enabled) crosses the V_{IN_TH}. During V_IN flash monitor there is a 8-µs deglitch time so the V_IN flash monitor flag is written (and the last flash register is updated) 8 µs after V_IN falls below V_{IN_FLASH}.

7.6.11 Torch Brightness Register Descriptions (Address 0xA0)

Bits [2:0] of the torch brightness register set the torch current for LED1. Bits [5:3] set the torch current for LED2 (see Table 13).

7.6.12 Flash Brightness Register (Address 0xB0)

Bits [3:0] of the flash brightness register set the flash current for LED1. Bits [7:4] set the flash current for LED2 (see Table 14).

7.6.13 Flash Duration Register (Address 0xC0)

Bits [4:0] of the flash duration register set the flash timeout duration. Bits [6:5] set the switch current limit (see Table 15).

7.6.14 Flags Register (Address 0xD0)

The flags register holds the flag bits indicating flash timeout, thermal shutdown, LED fault (open or short), TX interrupts (TX1 and TX2), LED thermal fault (NTC), V_IN monitor trip, and V_IN flash monitor trip. All flags are cleared on read back of the flags register. (See Table 16).

7.6.15 Configuration Register 1 (Address 0xE0)

Configuration register 1 holds the STROBE Enable bit, the STROBE polarity bit, the NTC Enable bit, the polarity selection bit for TX1 and TX2, and the hardware torch enable bit (see Table 17).

7.6.16 Configuration Register 2 (Address 0xF0)

Configuration register 2 holds the TX2 shutdown select bit, the NTC shutdown select bit, the AET mode select bit, the V_IN monitor shutdown bit, and the TX1 shutdown bit (see Table 18).