ZHCSIX9B october   2018  – october 2020 ISO1042-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Transient Immunity
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Ratings
    7. 6.7  Insulation Specifications
    8. 6.8  Safety-Related Certifications
    9. 6.9  Safety Limiting Values
    10. 6.10 Electrical Characteristics - DC Specification
    11. 6.11 Switching Characteristics
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Test Circuits
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CAN Bus States
      2. 8.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
      3. 8.3.3 Protection Features
        1. 8.3.3.1 TXD Dominant Timeout (DTO)
        2. 8.3.3.2 Thermal Shutdown (TSD)
        3. 8.3.3.3 Undervoltage Lockout and Default State
        4. 8.3.3.4 Floating Pins
        5. 8.3.3.5 Unpowered Device
        6. 8.3.3.6 CAN Bus Short Circuit Current Limiting
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bus Loading, Length and Number of Nodes
        2. 9.2.2.2 CAN Termination
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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6.11 Switching Characteristics

Over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DEVICE SWITCHING CHARACTERISTICS
tPROP(LOOP1)Total loop delay, driver input TXD to receiver RXD, recessive to dominantSee Figure 7-6, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V70125198.0ns
See Figure 7-6, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V70122192.0ns
tPROP(LOOP2)Total loop delay, driver input TXD to receiver RXD, dominant to recessiveSee Figure 7-6, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V70155215.0ns
See Figure 7-6, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V70152215.0ns
tUV_RE_ENABLERe-enable time after Undervoltage eventTime for device to return to normal operation from VCC1 or VCC2 under voltage event300.0µs
CMTICommon mode transient immunityVCM = 1200 VPK, See Figure 7-1085100kV/µs
DRIVER SWITCHING CHARACTERISTICS
tpHRPropagation delay time, HIGH TXD to driver recessiveSee Figure 7-3, RL = 60 Ω and CL = 100 pF; input rise/fall time (10% to 90%) on TXD =1 ns76120ns
tpLDPropagation delay time, LOW TXD to driver dominant61120
tsk(p)Pulse skew (|tpHR - tpLD|)14
tRDifferential output signal rise time45
tFDifferential output signal fall time45
VSYMOutput symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) / VCC2See Figure 7-3 and Figure 9-4 , RTERM = 60 Ω, CSPLIT = 4.7 nF, CL = open, RL = open, TXD = 250 kHz, 1 MHz0.91.1V/V
tTXD_DTODominant time outSee Figure 7-8, RL = 60 Ω and CL = open1.23.8ms
RECEIVER SWITCHING CHARACTERISTICS
tpRHPropagation delay time, bus recessive input to RXD high outputSee Figure 7-5, CL(RXD) = 15 pF75130ns
tpDLPropogation delay time, bus dominant input to RXD low output63130ns
tROutput signal rise time(RXD)1.4ns
tFOutput signal fall time(RXD)1.8ns
FD TIMING PARAMETERS
tBIT(BUS)Bit time on CAN bus output pins with tBIT(TXD) = 500 nsSee Figure 7-7, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns435.0530.0ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 nsSee Figure 7-7, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns155.0210.0ns
tBIT(RXD)Bit time on RXD output pins with tBIT(TXD) = 500 nsSee Figure 7-7, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns400550.0ns
Bit time on RXD output pins with tBIT(TXD) = 200 nsSee Figure 7-7, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns120.0220.0ns
∆tRECReceiver timing symmetry with tBIT(TXD) = 500 nsSee Figure 7-7, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS)-65.040.0ns
Receiver timing symmetry with tBIT(TXD) = 200 nsSee Figure 7-7, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns;  ΔtREC = tBIT(RXD) - tBIT(BUS)-45.015.0ns