ZHCS600D december   2011  – december 2020 HD3SS212

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Function
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1 Test Timing Diagrams
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 AC Coupling Caps
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11.   Power Supply Recommendations
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resource
    3. 11.3 Trademarks
  14. 12Mechanical, Packaging, and Orderable Information

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Overview

The HD3SS212 is a high-speed passive switch offered in an industry standard 48-pin u*BGA package available in a common footprint shared by several other vendors. The device is specified to operate from a single supply voltage of 3.3 V over the industrial temperature range of -40°C to 105°C.

The HD3SS212 is a generic 4-CH high-speed mux/demux type of switch that can be used for routing high-speed signals between two different locations on a circuit board. The HD3SS212 will also support several other high-speed data protocols with a differential amplitude of < 1800 mVpp and a common-mode voltage of < 2.0 V, as with USB 3.0 and DisplayPort 1.2. For Display Port Applications the HD3SS212 also supports switching of both the Auxiliary and Hot Plug Detect signals.

The device’s High Speed Port Selection Control input (Dx_SEL) pin can easily be controlled by an available GPIO pin within a system.