ZHCSIK8 July   2018 ESD351

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     典型的 USB 2.0 应用原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings -JEDEC Specifications
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 Electrical Characteristics

At TA = 25°C unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 50 nA, across operating temperature range 3.6 V
ILEAKAGE Leakage current at 3.6 V VIO = 3.6 V, I/O to GND 0.1 10 nA
VBRF Breakdown voltage, I/O to GND (1) IIO = 1 mA 4.5 7.5 V
VFWD Forward Voltage, GND to I/O (1) IIO = 1 mA 0.8 V
VHOLD Holding voltage, I/O to GND (2) IIO = 1 mA 5.1 V
VCLAMP Clamping voltage IPP = 6 A (8/20 µs Surge), I/O to GND 6.1 V
IPP = 16 A (100 ns TLP), I/O to GND 6.5 V
IPP = 16 A (100 ns TLP), GND to I/O 2.5 V
RDYN Dynamic resistance I/O to GND, 100 ns TLP, between 10 to 20 A IPP 0.1 Ω
GND to I/O , 100 ns TLP, between 10 to 20 A IPP 0.08
CLINE Line capacitance, IO to GND VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 1.8 2.2 pF
(1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state
(2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state.