ZHCSQI3A April   2022  – July 2022 ESD341

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1.     Absolute Maximum Ratings
    2. 6.1 ESD Ratings—JEDEC Specification
    3. 6.2 ESD Ratings—IEC Specification
    4.     Recommended Operating Conditions
    5. 6.3 Thermal Information
    6. 6.4 Electrical Characteristics
    7. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 ESD Protection
      2. 7.3.2 IEC 61000-4-5 Surge Protection
      3. 7.3.3 IO Capacitance
      4. 7.3.4 DC Breakdown Voltage
      5. 7.3.5 Ultra Low Leakage Current
      6. 7.3.6 Low ESD Clamping Voltage
      7. 7.3.7 Supports High Speed Interfaces
      8. 7.3.8 Industrial Temperature Range
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DPL|2
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.4 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VRWM Reverse stand-off voltage Pin 1 to Pin 2 or Pin 2 to Pin 1 -3.6 3.6 V
VBRF Break-down voltage IIO = 1 mA, Pin 1 to Pin 2 5 6.2 7.2 V
VBRR Break-down voltage IIO = -1 mA, Pin 2 to Pin 1 -7.2 -6.2 -5 V
VHOLD Holding voltage (1) TLP, Pin 1 to Pin 2 or Pin 2 to Pin 1  6.2 V
VClamp_TLP Clamp voltage with TLP (1) IPP = 1 A, TLP, Pin 1 to Pin 2 6.3 V
IPP = 5 A, TLP, Pin 1 to Pin 2 7.4
IPP = 16 A, TLP, Pin 1 to Pin 2 10.2
IPP = 1 A, TLP, Pin 2 to Pin 1 6.3
IPP = 5 A, TLP, Pin 2 to Pin 1 7.4
IPP =16 A, TLP, Pin 2 to Pin 1 10.2
VClamp_Surge Clamp voltage with surge strike (3) IPP = 5.4 A, tp = 8/20 µs , Pin 1 to Pin 2 or Pin 2 to Pin 1 8.8 V
ILEAK Leakage current VIO = 3.6 V, Pin 1 to Pin 2 or Pin 2 to Pin 1 5 100 nA
RDYN Dynamic resistance (2) Pin 1 to Pin 2 0.25 Ω
Pin 2 to Pin 1
CL Line capacitance VIO = 0 V;  ƒ = 1 MHz, Pin 1 to Pin 2, TA = 25℃ 0.66 pF
(1) Typical parameters are measured at 25℃
(2) Transition line pulse with 100 ns width and 10 ns rise and fall time
(3) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I = 20 A
(4) Nonrepetitive current pulse 8 to 20 µs exponentially decaying waveform according to IEC 61000-4-5