SNLS231O September   2006  – April 2015 DS90UR124-Q1 , DS90UR241-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Serializer Input Timing Requirements for TCLK
    7. 7.7 Serializer Switching Characteristics
    8. 7.8 Deserializer Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Initialization and Locking Mechanism
      2. 8.3.2  Data Transfer
      3. 8.3.3  Resynchronization
      4. 8.3.4  Powerdown
      5. 8.3.5  Tri-State
      6. 8.3.6  Pre-Emphasis
      7. 8.3.7  AC-Coupling and Termination
        1. 8.3.7.1 Receiver Termination Option 1
        2. 8.3.7.2 Receiver Termination Option 2
        3. 8.3.7.3 Receiver Termination Option 3
      8. 8.3.8  Signal Quality Enhancers
      9. 8.3.9  @SPEED-BIST Test Feature
      10. 8.3.10 Backward-Compatible Mode With DS90C241 and DS90C124
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using the DS90UR241 and DS90UR124
      2. 9.1.2 Display Application
      3. 9.1.3 Typical Application Connection
    2. 9.2 Typical Applications
      1. 9.2.1 DS90UR241-Q1 Typical Application Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Power Considerations
          2. 9.2.1.2.2 Noise Margin
          3. 9.2.1.2.3 Transmission Media
          4. 9.2.1.2.4 Live Link Insertion
        3. 9.2.1.3 Application Curves
      2. 9.2.2 DS90UR124 Typical Application Connection
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout and Power System Considerations
      2. 11.1.2 LVDS Interconnect Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

1 Features

  • Supports Displays With 18-Bit Color Depth
  • 5-MHz to 43-MHz Pixel Clock
  • Automotive-Grade Product AEC-Q100 Grade 2 Qualified
  • 24:1 Interface Compression
  • Embedded Clock With DC Balancing Supports AC-Coupled Data Transmission
  • Capable to Drive up to 10 Meters Shielded Twisted-Pair Cable
  • No Reference Clock Required (Deserializer)
  • Meets ISO 10605 ESD – Greater than 8 kV HBM ESD Structure
  • Hot Plug Support
  • EMI Reduction – Serializer Accepts Spread Spectrum Input; Data Randomization and Shuffling on Serial Link; Deserializer Provides Adjustable PTO (Progressive Turnon) LVCMOS Outputs
  • @Speed BIST (Built-In Self-Test) to Validate LVDS Transmission Path
  • Individual Power-Down Controls for Both Transmitter and Receiver
  • Power Supply Range 3.3 V ±10%
  • 48-Pin TQFP Package for Transmitter and 64-Pin TQFP Package for Receiver
  • Temperature Range: –40°C to 105°C
  • Backward-Compatible Mode With DS90C241/DS90C124

2 Applications

  • Automotive Central Information Displays
  • Automotive Instrument Cluster Displays
  • Automotive Heads-Up Displays
  • Remote Camera-Based Driver Assistance Systems

3 Description

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UR124-Q1 TQFP (64) 10.00 mm × 10.00 mm
DS90UR241-Q1 TQFP (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Applications Diagram

DS90UR124-Q1 DS90UR241-Q1 20194527.gif

Block Diagram

DS90UR124-Q1 DS90UR241-Q1 20194501.gif