ZHCSET3A November   2015  – December 2015 DS90CR286AT-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
        1. 7.3.1.1 Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Bit Resolution and Operating Frequency Compatibility
        2. 8.2.2.2 Data Mapping between Receiver and Endpoint Panel Display
        3. 8.2.2.3 RSKM Interoperability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DGG Package
56-Pin TSSOP
Top View
DS90CR286AT-Q1 10087323.png

Pin Functions

PIN I/O , TYPE PIN DESCRIPTION
NAME NO.
RxIN0+, RxIN0-,
RxIN1+, RxIN1-,
RxIN2+, RxIN2-,
RxIN3+, RxIN3-		 10, 9,
12, 11,
16, 15,
20, 19		 I, LVDS Positive and negative LVDS differential data inputs. 100 Ω termination resistors should be placed between RxIN+ and RxIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxCLKIN+,
RxCLKIN-		 18,
17		 I, LVDS Positive and negative LVDS differential clock input. 100 Ω termination resistor should be placed between RxCLKIN+ and RxCLKIN- receiver inputs as close as possible to the receiver pins for proper signaling.
RxOUT[27:0] 7, 6, 5, 3,
2, 1, 55, 54,
53, 51, 50, 49,
47, 46, 45, 43,
42, 41, 39, 38,
37, 35, 34, 33,
32, 30, 29, 27		 O, LVCMOS LVCMOS level data outputs.
RxCLK OUT 26 O, LVCMOS LVCMOS Ievel clock output. The rising edge acts as the data strobe.
PWR DWN 25 I, LVCMOS LVCMOS level input. When asserted low, the receiver outputs are low.
VCC 56, 48, 40, 31 Power Power supply pins for LVCMOS outputs.
GND 52, 44, 36,
28, 4		 Power Ground pins for LVCMOS outputs.
PLL VCC 23 Power Power supply for PLL.
PLL GND 24, 22 Power Ground pin for PLL.
LVDS VCC 13 Power Power supply pin for LVDS inputs.
LVDS GND 21, 14, 8 Power Ground pins for LVDS inputs.