SNLS055J November   1999  – May 2016 DS90CF366 , DS90CF386

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 LVDS Receivers
        1. 7.3.1.1 LVDS Input Termination
      2. 7.3.2 Phase Locked Loop (PLL)
      3. 7.3.3 Serial LVDS-to-Parallel LVCMOS Converter
      4. 7.3.4 LVCMOS Drivers
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Sequencing and Power-Down Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Cables
        2. 8.2.2.2 Bit Resolution and Operating Frequency Compatibility
        3. 8.2.2.3 Data Mapping between Receiver and Endpoint Panel Display
        4. 8.2.2.4 RSKM Interoperability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC –0.3 4 V
CMOS/LVCMOS output voltage –0.3 VCC + 0.3 V
LVDS receiver input voltage –0.3 VCC + 0.3 V
Power dissipation capacity at 25°C DS90CF366, TSSOP package 1.61 W
DS90CF386 TSSOP package 1.89
NFBGA package 2
Lead temperature TSSOP soldering (4 s) 260 °C
NFBGA soldering, reflow (20 s) 220
Operating junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±7000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±700
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
Receiver input 0 2.4 V
VNOISE Supply noise voltage 100 mVPP
TA Operating free-air temperature –10 25 70 °C

6.4 Thermal Information

THERMAL METRIC(1) DS90CF366 DS90CF386 UNIT
DGG (TSSOP) DGG (TSSOP) NZC (NFBGA)
48 PINS 56 PINS 64 PINS
RθJA Junction-to-ambient thermal resistance 67.8 64.6 65.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 22.1 20.6 23.8 °C/W
RθJB Junction-to-board thermal resistance 34.8 33.3 44.9 °C/W
ψJT Junction-to-top characterization parameter 1.1 1 1 °C/W
ψJB Junction-to-board characterization parameter 34.5 33 44.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
LVCMOS DC SPECIFICATIONS
VIH High level input voltage 2 VCC V
VIL Low level input voltage GND 0.8 V
VOH High level output voltage IOH = –0.4 mA 2.7 3.3 V
VOL Low level output voltage IOL = 2 mA 0.06 0.3 V
VCL Input clamp voltage ICL = –18 mA –0.79 –1.5 V
IIN Input current VIN = 0.4 V, 2.5 V or VCC 1.8 15 uA
VIN = GND –10 0 uA
IOS Output short circuit current VOUT = 0 V –60 –120 mA
LVDS RECEIVER DC SPECIFICATIONS
VTH Differential input high threshold V CM = 1.2 V 100 mV
VTL Differential input low threshold –100 mV
I IN Input current V IN = 2.4 V, VCC = 3.6 V ±10 μA
V IN = 0 V, VCC = 3.6 V ±10 μA
RECEIVER SUPPLY CURRENT
ICCRW Receiver supply current
worst case		 CL = 8 pF, worst case pattern, DS90CF386, see Figure 1 and Figure 4 f = 32.5 MHz 49 70 mA
f = 37.5 MHz 53 75 mA
f = 65 MHz 81 114 mA
f = 85 MHz 96 135 mA
CL = 8 pF, worst case pattern, DS90CF366, see Figure 1 and Figure 4 f = 32.5 MHz 49 60 mA
f = 37.5 MHz 53 65 mA
f = 65 MHz 78 100 mA
f = 85 MHz 90 115 mA
ICCRG Receiver supply current,
16 grayscale		 CL = 8 pF, 16 grayscale pattern, see Figure 2, Figure 3, and Figure 4 f = 32.5 MHz 28 45 mA
f = 37.5 MHz 30 47 mA
f = 65 MHz 43 60 mA
f = 85 MHz 43 70 mA
ICCRZ Receiver supply current
power down(2)		 Power Down = low receiver outputs stay low during power down mode 140 400 μA
(1) Typical values are given for VCC = 3.3 V and TA = 25°C.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ΔV OD).

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
CLHT CMOS or LVCMOS low-to-high transition time See Figure 4 2 3.5 ns
CHLT CMOS or LVCMOS high-to-low transition time See Figure 4 1.8 3.5 ns
RSPos0 Receiver input strobe position for bit 0 f = 85 MHz, see Figure 11 and Figure 12 0.49 0.84 1.19 ns
RSPos1 Receiver input strobe position for bit 1 f = 85 MHz 2.17 2.52 2.87 ns
RSPos2 Receiver input strobe position for bit 2 f = 85 MHz 3.85 4.2 4.55 ns
RSPos3 Receiver input strobe position for bit 3 f = 85 MHz 5.53 5.88 6.23 ns
RSPos4 Receiver input strobe position for bit 4 f = 85 MHz 7.21 7.56 7.91 ns
RSPos5 Receiver input strobe position for bit 5 f = 85 MHz 8.89 9.24 9.59 ns
RSPos6 Receiver input strobe position for bit 6 f = 85 MHz 10.57 10.92 11.27 ns
RSKM RxIN skew margin(2) f = 85 MHz, see Figure 13 290 ps
RCOP RxCLK OUT period See Figure 5 11.76 T 50 ns
RCOH RxCLK OUT high time f = 85 MHz, see Figure 5 4.5 5 7 ns
RCOL RxCLK OUT low time f = 85 MHz, see Figure 5 4 5 6.5 ns
RSRC RxOUT setup to RxCLK OUT f = 85 MHz, see Figure 5 2 ns
RHRC RxOUT hold to RxCLK OUT f = 85 MHz, see Figure 5 3.5 ns
RCCD RxCLK IN to RxCLK OUT delay 25°C, VCC = 3.3 V, see Figure 6 5.5 7 9.5 ns
RPLLS Receiver phase lock loop set See Figure 7 10 ms
RPDD Receiver power down delay See Figure 10 1 μs
(1) Typical values are given for VCC = 3.3 V and TA = 25°C.
(2) Receiver skew margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).

6.7 Timing Diagrams

DS90CF366 DS90CF386 10108502.png Figure 1. Test Pattern, Worst Case
DS90CF366 DS90CF386 10108512.png
1. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and CMOS or LVCMOS I/O.
2. The 16 grayscale test pattern tests device power consumption for a typical LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
3. Figure 1 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
4. Recommended pin to signal mapping. Customer may choose to define differently.
Figure 2. Test Pattern, 16 Grayscale (DS90CF386)
DS90CF366 DS90CF386 10108503.gif
1. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and CMOS or LVCMOS I/O.
2. The 16 grayscale test pattern tests device power consumption for a typical LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display.
3. Figure 1 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
4. Recommended pin to signal mapping. Customer may choose to define differently.
Figure 3. Test Pattern, 16 Grayscale (DS90CF366)
DS90CF366 DS90CF386 10108504.png Figure 4. DS90CF3x6 (Receiver) CMOS or LVCMOS Output Load and Transition Times
DS90CF366 DS90CF386 10108505.png Figure 5. DS90CF3x6 (Receiver) Setup or Hold and High or Low Times
DS90CF366 DS90CF386 10108506.png Figure 6. DS90CF3x6 (Receiver) Clock In to Clock Out Delay
DS90CF366 DS90CF386 10108507.png Figure 7. DS90CF3x6 (Receiver) Phase Lock Loop Set Time
DS90CF366 DS90CF386 10087309.gif Figure 8. DS90CF386 Mapping of 28 LVCMOS Parallel Data to 4D + C LVDS Serialzied Data
DS90CF366 DS90CF386 10087310.gif Figure 9. DS90CF366 Mapping of 21 LVCMOS Parallel Data to 3D + C LVDS Serialized Data
DS90CF366 DS90CF386 10108508.png Figure 10. DS90CF3x6 (Receiver) Power Down Delay
DS90CF366 DS90CF386 10108525.png Figure 11. DS90CF386 (Receiver) LVDS Input Strobe Position
DS90CF366 DS90CF386 10108526.png Figure 12. DS90CF366 (Receiver) LVDS Input Strobe Position
DS90CF366 DS90CF386 10108511.png
C: Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos: Transmitter output pulse position (min and max)
Cable skew: Typically 10 ps–40 ps per foot, media dependent
RSKM = Cable skew (type, length) + source clock jitter (cycle-to-cycle)(1) + ISI (inter-symbol interference)(2)
(1) Cycle-to-cycle jitter depends on the Tx source. Clock jitter should be maintained to less than 250 ps at 85 MHz.
(2) ISI is dependent on interconnect length; may be zero.
Figure 13. Receiver LVDS Input Skew Margin

6.8 Typical Characteristics

DS90CF366 DS90CF386 Typ_RxOUT_v_RxCLKOUT_85_MHz.gif Figure 14. Parallel PRBS-7 on LVCMOS Outputs at 85 MHz
DS90CF366 DS90CF386 RxOUT_Setup_to_RxCLKOUT_Time_85_MHz.gif Figure 16. Typical RxOUT Setup Time at 85 MHz
(RSRC = 4.5 ns)
DS90CF366 DS90CF386 Typ_RxOUT_Strobe_85_MHz.gif Figure 15. Typical RxOUT Strobe Position at 85 MHz
DS90CF366 DS90CF386 RxOUT_Hold_to_RxCLKOUT_Time_85_MHz.gif Figure 17. Typical RxOUT Hold Time at 85 MHz
(RHRC = 5.9 ns)