SNLS209M November   2005  – January 2017 DS90C124 , DS90C241

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements - Serializer
    7. 6.7 Switching Characteristics - Serializer
    8. 6.8 Switching Characteristics - Deserializer
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Initialization and Locking Mechanism
      2. 8.3.2 Data Transfer
      3. 8.3.3 Resynchronization
      4. 8.3.4 Pre-Emphasis
      5. 8.3.5 AC-Coupling and Termination
        1. 8.3.5.1 Receiver Termination Options
          1. 8.3.5.1.1 Option 1
            1. 8.3.5.1.1.1 Option 2
            2. 8.3.5.1.1.2 Option 3
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down
      2. 8.4.2 Tri-State
      3. 8.4.3 Progressive Turn-On (PTO)
  9. 9 Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Using the DS90C241 and DS90C124
      2. 9.1.2 Display Application
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Noise Margin
        2. 9.2.2.2 Transmission Media
        3. 9.2.2.3 Live Link Insertion
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 LVDS Interconnect Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.3 4 V
LVCMOS/LVTTL input voltage –0.3 VCC + 0.3 V
LVCMOS/LVTTL output voltage –0.3 VCC + 0.3 V
LVDS receiver input voltage –0.3 3.9 V
LVDS driver output voltage –0.3 3.9 V
LVDS output short circuit duration 10 ms
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±8000 V
Charged-device model (CDM), per AEC Q100-011 ±1250
RD = 330 Ω, CS = 150 pF IEC, powered-up only contact discharge (RIN0+, RIN0-, RIN1+, RIN1-) ±8000
IEC, powered-up only air-gap discharge (RIN0+, RIN0-, RIN1+, RIN1-) ±15000
RD = 330 Ω, CS = 150 and 330 pF ISO10605 contact discharge
(RIN0+, RIN0-, RIN1+, RIN1-) 		±8000
ISO10605 air-gap discharge
(RIN0+, RIN0-, RIN1+, RIN1-) 		±15000
RD = 2 kΩ, CS = 150 and 330 pF ISO10605 contact discharge
(RIN0+, RIN0-, RIN1+, RIN1-) 		±8000
ISO10605 air-gap discharge
(RIN0+, RIN0-, RIN1+, RIN1-) 		±15000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
Clock rate 5 35 MHz
Supply noise ±100 mVP-P
TA Operating free-air temperature −40 25 105 °C

6.4 Thermal Information

THERMAL METRIC(1) DS90C241-Q1
DS90C124-Q1		 UNIT
TFB (TQFP)
48 PINS
RθJA Junction-to-ambient thermal resistance 67.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.1 °C/W
RθJB Junction-to-board thermal resistance 33.4 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 33 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVCMOS AND LVTTL DC SPECIFICATIONS
VIH High-level voltage Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB, DCAOFF, DCBOFF, and VODSEL; and
Rx: RPWDNB, RRFB, and REN		 2 VCC V
VIL Low-level input voltage Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB, DCAOFF, DCBOFF, and VODSEL; and
Rx: RPWDNB, RRFB, and REN		 GND 0.8 V
VCL Input clamp voltage ICL = −18 mA, Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB, DCAOFF, DCBOFF, and VODSEL; and
Rx: RPWDNB, RRFB, and REN(1)		 −0.8 −1.5 V
IIN Input current VIN = 0 V or 3.6 V Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB, DCAOFF, DCBOFF, and VODSEL −10 ±5 10 µA
Rx: RPWDNB, RRFB, and REN −20 ±5 20
VOH High-level output voltage IOH = −4 mA, Rx: ROUT[23:0], RCLK, and LOCK 2.3 3 VCC V
VOL Low-level output voltage IOL = 4 mA, Rx: ROUT[23:0], RCLK, and LOCK GND 0.33 0.5 V
IOS Output short circuit current VOUT = 0 V, Rx: ROUT[23:0], RCLK, and LOCK(1) −40 −70 −110 mA
IOZ TRI-STATE output current RPWDNB, REN = 0 V, VOUT = 0 V or 2.4 V,
Rx: ROUT[23:0], RCLK, and LOCK		 −30 ±0.4 30 µA
LVDS DC SPECIFICATIONS
VTH Differential threshold high voltage VCM = 1.2 V, Rx: RIN+ and RIN− 50 mV
VTL Differential threshold low voltage Rx: RIN+ and RIN− −50 mV
IIN Input current VIN = 2.4 V, VCC = 3.6 V or 0 V, Rx: RIN+ and RIN− ±200 µA
VIN = 0 V, VCC = 3.6 V, Rx: RIN+ and RIN− ±200
VOD Output differential voltage
(DOUT+) – (DOUT−) 		RL = 100 Ω, without pre-emphasis, Tx: DOUT+ and DOUT− (see Figure 12) VODSEL = L 250 400 600 mV
VODSEL = H 450 750 1200
ΔVOD Output differential voltage unbalance RL = 100 Ω, without pre-emphasis, Tx: DOUT+ and DOUT− 10 50 mV
VOS Offset voltage RL = 100 Ω, without pre-emphasis, Tx: DOUT+ and DOUT− 1 1.25 1.5 V
ΔVOS Offset voltage unbalance RL = 100 Ω, without pre-emphasis, Tx: DOUT+ and DOUT− 1 50 mV
IOS Output short circuit current DOUT = 0 V, DIN = H, TPWDNB, DEN = 2.4 V,
Tx: DOUT+ and DOUT−		 VODSEL = L −2 −8 mA
DOUT = 0 V, DIN = H, TPWDNB, DEN = 2.4 V,
Tx: DOUT+ and DOUT−		 VODSEL = H −7 −13
IOZ TRI-STATE output current TPWDNB, DEN = 0 V, DOUT = 0 V or 2.4 V,
Tx: DOUT+ and DOUT−		 −15 ±1 15 µA
SERIALIZER OR DESERIALIZER SUPPLY CURRENT – DVDDx, PVDDx, AND AVDDx PINS (Digital, PLL, and Analog VDDs)
ICCT Serializer (Tx) total supply current (includes load current) RL = 100 Ω, RPRE = OFF, VODSEL = H/L, f = 35 MHz, and checker-board pattern (see Figure 3) 40 65 mA
RL = 100 Ω, RPRE = 6 kΩ, VODSEL = H/L, f = 35 MHz, and checker-board pattern (see Figure 3) 45 70 mA
Serializer (Tx) total supply current (includes load current) f = 35 MHz, RL = 100 Ω, RPRE = OFF,
and VODSEL = H/L		 40 65 mA
f = 35 MHz, RL = 100 Ω, RPRE = 6 kΩ, VODSEL = H/L, and random pattern 45 70 mA
ICCTZ Serializer (Tx) supply current power-down TPWDNB = 0 V (all other LVCMOS inputs = 0 V) 800 µA
ICCR Deserializer (Rx) total supply current (includes load current) CL = 8-pF LVCMOS output, f = 35 MHz, and checker-board pattern (see Figure 4) 85 mA
Deserializer (Rx) total supply current (includes load current) CL = 8-pF LVCMOS output, f = 35 MHz, and random pattern 80 mA
ICCRZ Deserializer (Rx) supply current power-down RPWDNB = 0 V (all other LVCMOS inputs = 0 V,
RIN+/ RIN– = 0 V)		 50 µA
(1) Specification is ensured by characterization and is not tested in production.

6.6 Timing Requirements – Serializer

over recommended operating supply and temperature ranges (unless otherwise noted)
MIN TYP MAX UNIT
tTCP Transmit clock period (see Figure 7) 28.6 T 200 ns
tTCIH Transmit clock high time 0.4T 0.5T 0.6T ns
tTCIL Transmit clock low time 0.4T 0.5T 0.6T ns
tCLKT TCLK input transition time (see Figure 6) 3 6 ns
tJIT TCLK input jitter(1) 33 ps (RMS)
(1) tJIT (at BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.

6.7 Switching Characteristics – Serializer

over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLLHT LVDS Low-to-High transition time RL = 100 Ω, CL = 10 pF to GND, and VODSEL = L (see Figure 5) 0.6 ns
tLHLT LVDS High-to-Low transition time RL = 100 Ω, CL = 10 pF to GND, and VODSEL = L (see Figure 5) 0.6 ns
tDIS DIN[23:0] setup to TCLK RL = 100 Ω and CL = 10 pF to GND(1) 5 ns
tDIH DIN[23:0] hold from TCLK RL = 100 Ω and CL = 10 pF to GND(1) 5 ns
tHZD DOUT± HIGH to TRI-STATE delay RL = 100 Ω and CL = 10 pF to GND
(see Figure 8)(2)		 15 ns
tLZD DOUT± LOW to TRI-STATE delay RL = 100 Ω and CL = 10 pF to GND
(see Figure 8)(2)		 15 ns
tZHD DOUT± TRI-STATE to HIGH delay RL = 100 Ω and CL = 10 pF to GND
(see Figure 8)(2)		 200 ns
tZLD DOUT± TRI-STATE to LOW delay RL = 100 Ω and CL = 10 pF to GND
(see Figure 8)(2)		 200 ns
tPLD Serializer PLL lock time RL = 100 Ω (see Figure 9) 10 ms
tSD Serializer delay RL = 100 Ω, VODSEL = L, and TRFB = H
(see Figure 10) 		3.5T + 2.85 3.5T + 10 ns
RL = 100 Ω, VODSEL = L, and TRFB = L
(see Figure 10) 		3.5T + 2.85 3.5T + 10 ns
TxOUT_E_O TxOUT_Eye_Opening (respect to ideal) 5 MHz to 35 MHz (see Figure 11)(1)(3)(4) 0.75 UI(5)
(1) Specification is ensured by characterization and is not tested in production.
(2) When the serializer output is tri-stated, the deserializer loses PLL lock. Resynchronization must occur before data transfer.
(3) tJIT (at BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
(4) TxOUT_E_O is affected by pre-emphasis value.
(5) UI – Unit Interval; equivalent to one ideal serialized data bit width. The UI scales with frequency.

6.8 Switching Characteristics – Deserializer

over recommended operating supply and temperature ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tRCP Receiver out clock period tRCP = tTCP and RCLK pin(1) 28.6 200 ns
tRDC RCLK duty cycle RCLK pin 45% 50% 55%
tCLH LVCMOS low-to-high transition time CL = 8 pF (lumped load); ROUT[23:0], LOCK, and RCLK pins (see Figure 13)(1) 2.5 3.5 ns
tCHL LVCMOS high-to-low transition time CL = 8 pF (lumped load); ROUT[23:0], LOCK, and RCLK pins (see Figure 13)(1) 2.5 3.5 ns
tROS ROUT[7:0] setup data to RCLK (Group 1) ROUT[7:0] pins (see Figure 17) 0.4 × tRCP (29/56) × tRCP ns
tROH ROUT[7:0] hold data to RCLK (Group 1) ROUT[7:0] pins (see Figure 17) 0.4 × tRCP (27/56) × tRCP ns
tROS ROUT[15:8] setup data to RCLK (Group 2) ROUT[15:8] and LOCK pins (see Figure 17) 0.4 × tRCP 0.5 × tRCP ns
tROH ROUT[15:8] hold data to RCLK (Group 2) ROUT[15:8] and LOCK pins (see Figure 17) 0.4 × tRCP 0.5 × tRCP ns
tROS ROUT[23:16] setup data to RCLK (Group 3) ROUT[23:16] pins
(see Figure 17)		 0.4 × tRCP (27/56) × tRCP ns
tROH ROUT[23:16] hold data to RCLK (Group 3) ROUT[23:16] pins
(see Figure 17)		 0.4 × tRCP (29/56) × tRCP ns
tHZR HIGH to TRI-STATE delay ROUT[23:0], RCLK, and LOCK pins (see Figure 15) 3 10 ns
tLZR LOW to TRI-STATE delay ROUT[23:0], RCLK, and LOCK pins 3 10 ns
tZHR TRI-STATE to HIGH delay ROUT[23:0], RCLK, and LOCK pins 3 10 ns
tZLR TRI-STATE to LOW delay ROUT[23:0], RCLK, and LOCK pins 3 10 ns
tDD Deserializer delay RCLK pin (see Figure 14) [4+(3/56)]T + 5.9 [4+(3/56)]T + 14 ns
tDRDL Deserializer PLL lock time from power down See Figure 16(1)(2) 5 MHz 5 50 ms
35 MHz 5 50
RxIN_TOL_L Receiver input tolerance (left) 5 MHz to 35 MHz
(see Figure 18)(1)(3)		 0.25 UI(4)
RxIN_TOL_R Receiver input tolerance (right) 5 MHz to 35 MHz
(see Figure 18)(1)(3)		 0.25 UI(4)
(1) Specification is ensured by characterization and is not tested in production.
(2) The deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern.
(3) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement in reference with the ideal bit position. See AN-1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (SNLA053) for details.
(4) UI – Unit Interval; equivalent to one ideal serialized data bit width. The UI scales with frequency.

6.9 Typical Characteristics

Figure 1 and Figure 2 are scope shots with PCLK = 5 MHz measured out of the DS90C241 DOUT± with pre-emphasis OFF and pre-emphasis ON using a 1010... pattern on the DIN[23:0] inputs. The scope was triggered on the input PCLK.
DS90C124 DS90C241 C241_example_eye_at_5MHz.gif Figure 1. DS90C241 DOUT± Eye Diagram at 5 MHz
Without Pre-Emphasis
DS90C124 DS90C241 C241_example_eye_w_pre_at_5MHz.gif Figure 2. DS90C241 DOUT± Eye Diagram at 5 MHz
With Pre-Emphasis ON