SNLS334G April   2011  – January 2015 DS80PCI800

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Electrical Characteristics
    5. 6.5 Electrical Characteristics — Serial Management Bus Interface
    6. 6.6 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 4-Level Input Configuration Guidelines
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBUS Mode
    5. 8.5 Programming
      1. 8.5.1 System Management Bus (SMBus) and Configuration Registers
      2. 8.5.2 Transfer of Data Through the SMBus
      3. 8.5.3 Writing a Register
      4. 8.5.4 Reading a Register
      5. 8.5.5 SMBus Master Mode
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DS80PCI800 versus DS80PCI810
      2. 9.1.2 Signal Integrity in PCIe Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 3.3-V or 2.5-V Supply Mode Operation
    2. 10.2 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Considerations for Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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10 Power Supply Recommendations

10.1 3.3-V or 2.5-V Supply Mode Operation

The DS80PCI800 has an optional internal voltage regulator to provide the 2.5 V supply to the device. In 3.3-V mode, the VIN pin = 3.3 V is used to supply power to the device and the VDD pins should be left open. The internal regulator will provide the 2.5 V to the VDD pins of the device and a 0.1 μF cap is needed at each of the five VDD pins for power supply de-coupling (total capacitance should be ≤ 0.5 µF), and the VDD pins should be left open. The VDD_SEL pin must be tied to GND to enable the internal regulator. In 2.5-V mode, the VIN pin should be left open and 2.5 V supply must be applied to the VDD pins. The VDD_SEL pin must be left open (no connect) to disable the internal regulator.

The DS80PCI800 can be configured for 2.5 V operation or 3.3 V operation. The lists below outline required connections for each supply selection.

3.3-V Mode of Operation

  1. Tie VDD_SEL = 0 with 1-kΩ resistor to GND.
  2. Feed 3.3-V supply into VIN pin. Local 1.0-µF decoupling at VIN is recommended.
  3. See information on VDD bypass below.
  4. SDA and SCL pins should connect pullup resistor to VIN
  5. Any 4-Level input which requires a connection to "Logic 1" should use a 1-kΩ resistor to VIN

2.5-V Mode of Operation

  1. VDD_SEL = Float
  2. VIN = Float
  3. Feed 2.5-V supply into VDD pins.
  4. See information on VDD bypass below.
  5. SDA and SCL pins connect pullup resistor to VDD for 2.5-V uC SMBus IO
  6. SDA and SCL pins connect pullup resistor to VDD for 3.3-V uC SMBus IO
  7. Any 4-Level input which requires a connection to "Logic 1" should use a 1-kΩ resistor to VIN
30133306.gifFigure 14. 3.3 V or 2.5 V Supply Connection Diagram

10.2 Power Supply Bypassing

Two approaches are recommended to ensure that the DS80PCI800 is provided with an adequate power supply bypass. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. Second, careful attention to supply bypassing through the proper use of bypass capacitors is required. A 0.1-μF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to the device. Small body size capacitors (such as 0402) reduce the parasitic inductance of the capacitor and also help in placement close to the VDD pin. If possible, the layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance.