ZHCSQD1 August   2022 DS320PR810

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Reach Extension – x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.5.2.1 Shared Registers

Table 7-6 General Registers (Offset = 0xE2)
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 rst_i2c_regs R/W/SC 0x0 Device reset control: Reset all I2C registers to default values (self-clearing).
5 rst_i2c_mas R/W/SC 0x0 Reset I2C Primary (self-clearing).
4-1 RESERVED R 0x0 Reserved
0 frc_eeprm_rd R/W/SC 0x0 Override MODE and READ_EN_N status to force manual EEPROM configuration load.
Table 7-7 EEPROM_Status Register (Offset = 0xE3)
Bit Field Type Reset Description
7 eecfg_cmplt R 0x0 EEPROM load complete.
6 eecfg_fail R 0x0 EEPROM load failed.
5 eecfg_atmpt_1 R 0x0 Number of attempts made to load EEPROM image.
4 eecfg_atmpt_0 R 0x0 see MSB
3 eecfg_cmplt R 0x0 EEPROM load complete 2.
2 eecfg_fail R 0x0 EEPROM load failed 2.
1 eecfg_atmpt_1 R 0x0 Number of attempts made to load EEPROM image 2.
0 eecfg_atmpt_0 R 0x0 see MSB
Table 7-8 DEVICE_ID0 Register (Offset = 0xF0)
Bit Field Type Reset Description
7-4 RESERVED R 0x0 Reserved
3 device_id0_3 R 0x0 Device ID0 [3:1]: 011
2 device_id0_2 R 0x1 see MSB
1 device_id0_1 R 0x1 see MSB
0 RESERVED R X Reserved
Table 7-9 DEVICE_ID1 Register (Offset = 0xF1)
Bit Field Type Reset Description
7 device_id[7] R 0x0 Device ID 0010 1001: DS320PR810
6 device_id[6] R 0x0 see MSB
5 device_id[5] R 0x1 see MSB
4 device_id[4] R 0x0 see MSB
3 device_id[3] R 0x1 see MSB
2 device_id[2] R 0x0 see MSB
1 device_id[1] R 0x0 see MSB
0 device_id[0] R 0x0 see MSB