ZHCSQD1 August   2022 DS320PR810

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Jitter Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 Flat-Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Pin mode
        1. 7.5.1.1 Five-Level Control Inputs
      2. 7.5.2 SMBUS/I2C Register Control Interface
        1. 7.5.2.1 Shared Registers
        2. 7.5.2.2 Channel Registers
      3. 7.5.3 SMBus/I 2 C Primary Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Reach Extension – x16 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.5.2.2 Channel Registers

Table 7-10 RX Detect Status Register (Channel register base + Offset = 0x00)
Bit Field Type Reset Description
7 rx_det_comp_p R 0x0 Rx Detect positive data pin status:

0: Not detected

1: Detected – the value is latched
6 rx_det_comp_n R 0x0 Rx Detect negative data pin status:

0: Not detected

1: Detected – the value is latched
5-0 RESERVED R 0x0 Reserved
Table 7-11 EQ Gain Control Register (Channel register base + Offset = 0x01)
Bit Field Type Reset Description
7 eq_stage1_bypass R/W 0x0

Enable EQ stage 1 bypass:

0: Bypass disabled

1: Bypass enabled
6 eq_stage1_3 R/W 0x0

EQBoost stage 1 control

See Table 7-1 for details
5 eq_stage1_2 R/W 0x0
4 eq_stage1_1 R/W 0x0
3 eq_stage1_0 R/W 0x0
2 eq_stage2_2 R/W 0x0

EQ Boost stage 2 control

See Table 7-1 for details
1 eq_stage2_1 R/W 0x0
0 eq_stage2_0 R/W 0x0
Table 7-12 EQ Gain / Flat Gain Control Register (Channel register base + Offset = 0x03)
Bit Field Type Reset Description
7 RESERVED R 0x0 Reserved
6 eq_profile_3 R/W 0x0

EQ mid-frequency boost profile

See Table 7-1 for details

5 eq_profile_2 R/W 0x0
4 eq_profile_1 R/W 0x0
3 eq_profile_0 R/W 0x0
2 flat_gain_2 R/W 0x1

Flat gain select:

See Table 7-2 for details

1 flat_gain_1 R/W 0x0
0 flat_gain_0 R/W 0x1
Table 7-13 RX Detect Control Register (Channel register base + Offset = 0x04)
Bit Field Type Reset Description
7-3 RESERVED R 0x0 Reserved
2 mr_rx_det_man R/W 0x0

Manual override of rx_detect_p/n decision:

0: rx detect state machine is enabled

1: rx detect state machine is overridden – always valid RX termination detected
1 en_rx_det_count R/W 0x0 Enable additional RX detect polling

0: Additional RX detect polling disabled

1: Additional RX detect polling enabled
0 sel_rx_det_count R/W 0x0

Select number of valid RX detect polls – gated by en_rx_det_count = 1

0: Device transmitters poll until 2 consecutive valid detections

1: Device transmitters poll until 3 consecutive valid detections
Table 7-14 PD Override Register (Channel register base + Offset = 0x05)
Bit Field Type Reset Description
7 device_en_override R/W 0x0 Enable power down overrides thorugh SMBus/I2C

0: Manual override disabled

1: Manual override enabled
6-0 device_en R/W 0x111111 Manual power down of redriver various blocks – gated by device_en_override = 1

111111: All blocks are enabled

000000: All blocks are disabled
Table 7-15 Bias Register (Channel register base + Offset = 0x06)
Bit Field Type Reset Description
5-3 Bias current R/W 0x100 Control bias current

Set 001 for best performance
7,6,2-0 Reserved R/W 0x00000 Reserved