ZHCSJB5B September   2019  – December 2019 DRV8904-Q1 , DRV8906-Q1 , DRV8908-Q1 , DRV8910-Q1 , DRV8912-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     简化原理图
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions—DRV8912-Q1
    2.     Pin Functions—DRV8910-Q1
    3.     Pin Functions—DRV8908-Q1
    4.     Pin Functions—DRV8906-Q1
    5.     Pin Functions—DRV8904-Q1
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Half Bridge Drivers
        1. 8.3.1.1 Control Modes
          1. 8.3.1.1.1 Continuous Mode (Without PWM)
          2. 8.3.1.1.2 Chopping Mode (With PWM)
            1. 8.3.1.1.2.1 PWM Configuration
            2. 8.3.1.1.2.2 Free-Wheeling Mode (Synchronous Rectification) Disable / Enable
            3. 8.3.1.1.2.3 PWM Channels Mapping
            4. 8.3.1.1.2.4 PWM Channels Configuration (PWM Frequency and PWM Duty)
            5. 8.3.1.1.2.5 Half-Bridge Enable
          3. 8.3.1.1.3 Parallel Mode (Continuous Operation)
          4. 8.3.1.1.4 Parallel Mode (PWM Operation)
            1. 8.3.1.1.4.1 PWM Configuration
            2. 8.3.1.1.4.2 Free-Wheeling Mode (Synchronous Rectification) Disable / Enable
            3. 8.3.1.1.4.3 PWM Channels Mapping
            4. 8.3.1.1.4.4 PWM Channels Configuration (PWM Frequency and PWM Duty)
            5. 8.3.1.1.4.5 PWM Generators Disable
            6. 8.3.1.1.4.6 Half-Bridge Enable
            7. 8.3.1.1.4.7 PWM Generators Enable
        2. 8.3.1.2 Half-Bridge Drive Architecture
          1. 8.3.1.2.1 Slew Rate
          2. 8.3.1.2.2 Cross Conduction (Dead Time)
          3. 8.3.1.2.3 Propagation Delay
      2. 8.3.2 Pin Diagrams
        1. 8.3.2.1 Logic Level Input Pin (nSLEEP, SCLK and SDI)
        2. 8.3.2.2 Logic Level Input Pin (nSCS)
        3. 8.3.2.3 Open Drain Output Pin (nFAULT)
        4. 8.3.2.4 Push Pull Output Pin (SDO)
      3. 8.3.3 Protection Circuits
        1. 8.3.3.1 VM Supply Undervoltage Lockout (UVLO)
        2. 8.3.3.2 VM Supply Overvoltage Protection (OVP)
        3. 8.3.3.3 Logic Supply Power on Reset (POR)
        4. 8.3.3.4 Overcurrent Protection (OCP)
        5. 8.3.3.5 Open-load detection (OLD)
          1. 8.3.3.5.1 Active OLD
            1. 8.3.3.5.1.1 Negative-current OLD
          2. 8.3.3.5.2 Low-current OLD
          3. 8.3.3.5.3 Passive OLD
        6. 8.3.3.6 Thermal Warning (OTW)
        7. 8.3.3.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode (nSLEEP = 0)
      2. 8.4.2 Operating Mode (nSLEEP = 1)
      3. 8.4.3 Fault Mode
    5. 8.5 Programming
      1. 8.5.1 SPI
      2. 8.5.2 SPI Format
      3. 8.5.3 SPI Interface for Multiple Slaves
        1. 8.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 8.6 Register Map
      1. 8.6.1 DRV8912-Q1 and DRV8910-Q1 Register Maps
        1. 8.6.1.1 Status Registers
          1. 8.6.1.1.1 IC Status (IC_STAT) Register (Address = 0x00) [reset = 0x00]
            1. Table 20. IC Status Register Field Descriptions
          2. 8.6.1.1.2 Overcurrent Protection (OCP) Status 1 (OCP_STAT_1) Register (Address = 0x01) [reset = 0x00]
            1. Table 21. Overcurrent Protection (OCP) Status 1 Register Field Descriptions
          3. 8.6.1.1.3 Overcurrent Protection (OCP) Status 2 (OCP_STAT_2) Register (Address = 0x02) [reset = 0x00]
            1. Table 22. Overcurrent Protection (OCP) Status 2 Register Field Descriptions
          4. 8.6.1.1.4 Overcurrent Protection (OCP) Status 3 (OCP_STAT_3) Register (Address = 0x03) [reset = 0x00]
            1. Table 23. Overcurrent Protection (OCP) Status 3 Register Field Descriptions
          5. 8.6.1.1.5 Open-Load Detect (OLD) Status 1 (OLD_STAT_1) Register (Address = 0x04) [reset = 0x00]
            1. Table 24. Open-Load Detect (OLD) Status 1 Register Field Descriptions
          6. 8.6.1.1.6 Open-Load Detect (OLD) Status 2 (OLD_STAT_2) Register (Address = 0x05) [reset = 0x00]
            1. Table 25. Open-Load Detect (OLD) Status 2 Register Field Descriptions
          7. 8.6.1.1.7 Open-Load Detect (OLD) Status 3 (OLD_STAT_3) Register (Address = 0x06) [reset = 0x00]
            1. Table 26. Open-Load Detect (OLD) Status 3 Register Field Descriptions
        2. 8.6.1.2 Control Registers
          1. 8.6.1.2.1  Configuration (CONFIG_CTRL) Register (Address = 0x07) [reset = 0x00]
            1. Table 28. Configuration Register Field Descriptions
          2. 8.6.1.2.2  Operation Control 1 (OP_CTRL_1) Register (Address = 0x08) [reset = 0x00]
            1. Table 29. Operation Control 1 Register Field Descriptions
          3. 8.6.1.2.3  Operation Control 2 (OP_CTRL_2) Register (Address = 0x09) [reset = 0x00]
            1. Table 30. Operation Control 2 Register Field Descriptions
          4. 8.6.1.2.4  Operation Control 3 (OP_CTRL_3) Register (Address = 0x0A) [reset = 0x00]
            1. Table 31. Operation Control 3 Register Field Descriptions
          5. 8.6.1.2.5  PWM Control 1 (PWM_CTRL_1) Register (Address = 0x0B) [reset = 0x00]
            1. Table 32. PWM Control 1 Register Field Descriptions
          6. 8.6.1.2.6  PWM Control 2 (PWM_CTRL_2) Register (Address = 0x0C) [reset = 0x00]
            1. Table 33. PWM Control 2 Register Field Descriptions
          7. 8.6.1.2.7  Free-Wheeling Control 1 (FW_CTRL_1) Register (Address = 0x0D) [reset = 0x00]
            1. Table 34. Free-Wheeling Control 1 Register Field Descriptions
          8. 8.6.1.2.8  Free-Wheeling Control 2 (FW_CTRL_2) Register (Address = 0x0E) [reset = 0x00]
            1. Table 35. Free-Wheeling Control 2 Register Field Descriptions
          9. 8.6.1.2.9  PWM Map Control 1 (PWM_MAP_CTRL_1) Register (Address = 0x0F) [reset = 0x00]
            1. Table 36. PWM Map Control 1 Register Field Descriptions
          10. 8.6.1.2.10 PWM Map Control 2 (PWM_MAP_CTRL_2) Register (Address = 0x10) [reset = 0x00]
            1. Table 37. PWM Map Control 2 Register Field Descriptions
          11. 8.6.1.2.11 PWM Map Control 3 (PWM_MAP_CTRL_3) Register (Address = 0x11) [reset = 0x00]
            1. Table 38. PWM Map Control 3 Register Field Descriptions
          12. 8.6.1.2.12 PWM Frequency Control (PWM_FREQ_CTRL) Register (Address = 0x12) [reset = 0x00]
            1. Table 39. PWM Frequency Control Register Field Descriptions
          13. 8.6.1.2.13 PWM Duty Control Channel 1 (PWM_DUTY_CH1) Register (Address = 0x13) [reset = 0x00]
            1. Table 40. PWM Duty Control Channel 1 Register Field Descriptions
          14. 8.6.1.2.14 PWM Duty Control Channel 2 (PWM_DUTY_CH2) Register (Address = 0x14) [reset = 0x00]
            1. Table 41. PWM Duty Control Channel 2 Register Field Descriptions
          15. 8.6.1.2.15 PWM Duty Control Channel 3 (PWM_DUTY_CH3) Register (Address = 0x15) [reset = 0x00]
            1. Table 42. PWM Duty Control Channel 3 Register Field Descriptions
          16. 8.6.1.2.16 PWM Duty Control Channel 4 (PWM_DUTY_CH4) Register (Address = 0x16) [reset = 0x00]
            1. Table 43. PWM Duty Control Channel 4 Register Field Descriptions
          17. 8.6.1.2.17 Slew Rate Control 1 (SR_CTRL_1) Register (Address = 0x17) [reset = 0x00]
            1. Table 44. Slew Rate Control 1 Register Field Descriptions
          18. 8.6.1.2.18 Slew Rate Control 2 (SR_CTRL_2) Register (Address = 0x18) [reset = 0x00]
            1. Table 45. Slew Rate Control 2 Register Field Descriptions
          19. 8.6.1.2.19 Open-Load Detect (OLD) Control 1 (OLD_CTRL_1) Register (Address = 0x19) [reset = 0x00]
            1. Table 46. Open-Load Detect (OLD) Control (OLD_CTRL_1) Register Field Descriptions
          20. 8.6.1.2.20 Open-Load Detect (OLD) Control 2 (OLD_CTRL_2) Register (Address = 0x1A) [reset = 0x00]
            1. Table 47. Open-Load Detect (OLD) Control (OLD_CTRL_2) Register Field Descriptions
          21. 8.6.1.2.21 Open-Load Detect (OLD) Control 3 (OLD_CTRL_3) Register (Address = 0x1B) [reset = 0x00]
            1. Table 48. Open-Load Detect (OLD) Control (OLD_CTRL_3) Register Field Descriptions
          22. 8.6.1.2.22 Open-Load Detect (OLD) Control 4 (OLD_CTRL_4) Register (Address = 0x24) [reset = 0x00]
            1. Table 49. Open-Load Detect (OLD) Control (OLD_CTRL_4) Register Field Descriptions
      2. 8.6.2 DRV8908-Q1, DRV8906-Q1 and DRV8904-Q1 Register Maps
        1. 8.6.2.1 Status Registers
          1. 8.6.2.1.1 IC Status (IC_STAT) Register (Address = 0x00) [reset = 0x00]
            1. Table 54. IC Status Register Field Descriptions
          2. 8.6.2.1.2 Overcurrent Protection (OCP) Status 1 (OCP_STAT_1) Register (Address = 0x01) [reset = 0x00]
            1. Table 55. Overcurrent Protection (OCP) Status 1 Register Field Descriptions
          3. 8.6.2.1.3 Overcurrent Protection (OCP) Status 2 (OCP_STAT_2) Register (Address = 0x02) [reset = 0x00]
            1. Table 56. Overcurrent Protection (OCP) Status 2 Register Field Descriptions
          4. 8.6.2.1.4 Overcurrent Protection (OCP) Status 3 (OCP_STAT_3) Register (Address = 0x03) [reset = 0x00]
            1. Table 57. Overcurrent Protection (OCP) Status 3 Register Field Descriptions
          5. 8.6.2.1.5 Open-Load Detect (OLD) Status 1 (OLD_STAT_1) Register (Address = 0x04) [reset = 0x00]
            1. Table 58. Open-Load Detect (OLD) Status 1 Register Field Descriptions
          6. 8.6.2.1.6 Open-Load Detect (OLD) Status 2 (OLD_STAT_2) Register (Address = 0x05) [reset = 0x00]
            1. Table 59. Open-Load Detect (OLD) Status 2 Register Field Descriptions
          7. 8.6.2.1.7 Open-Load Detect (OLD) Status 3 (OLD_STAT_3) Register (Address = 0x06) [reset = 0x00]
            1. Table 60. Open-Load Detect (OLD) Status 3 Register Field Descriptions
        2. 8.6.2.2 Control Registers
          1. 8.6.2.2.1  Configuration (CONFIG_CTRL) Register (Address = 0x07) [reset = 0x00]
            1. Table 62. Configuration Register Field Descriptions
          2. 8.6.2.2.2  Operation Control 1 (OP_CTRL_1) Register (Address = 0x08) [reset = 0x00]
            1. Table 63. Operation Control 1 Register Field Descriptions
          3. 8.6.2.2.3  Operation Control 2 (OP_CTRL_2) Register (Address = 0x09) [reset = 0x00]
            1. Table 64. Operation Control 2 Register Field Descriptions
          4. 8.6.2.2.4  Operation Control 3 (OP_CTRL_3) Register (Address = 0x0A) [reset = 0x00]
            1. Table 65. Operation Control 3 Register Field Descriptions
          5. 8.6.2.2.5  PWM Control 1 (PWM_CTRL_1) Register (Address = 0x0B) [reset = 0x00]
            1. Table 66. PWM Control 1 Register Field Descriptions
          6. 8.6.2.2.6  PWM Control 2 (PWM_CTRL_2) Register (Address = 0x0C) [reset = 0x00]
            1. Table 67. PWM Control 2 Register Field Descriptions
          7. 8.6.2.2.7  Free-Wheeling Control 1 (FW_CTRL_1) Register (Address = 0x0D) [reset = 0x00]
            1. Table 68. Free-Wheeling Control 1 Register Field Descriptions
          8. 8.6.2.2.8  Free-Wheeling Control 2 (FW_CTRL_2) Register (Address = 0x0E) [reset = 0x00]
            1. Table 69. Free-Wheeling Control 2 Register Field Descriptions
          9. 8.6.2.2.9  PWM Map Control 1 (PWM_MAP_CTRL_1) Register (Address = 0x0F) [reset = 0x00]
            1. Table 70. PWM Map Control 1 Register Field Descriptions
          10. 8.6.2.2.10 PWM Map Control 2 (PWM_MAP_CTRL_2) Register (Address = 0x10) [reset = 0x00]
            1. Table 71. PWM Map Control 2 Register Field Descriptions
          11. 8.6.2.2.11 PWM Map Control 3 (PWM_MAP_CTRL_3) Register (Address = 0x11) [reset = 0x00]
            1. Table 72. PWM Map Control 3 Register Field Descriptions
          12. 8.6.2.2.12 PWM Map Control 4 (PWM_MAP_CTRL_4) Register (Address = 0x12) [reset = 0x00]
            1. Table 73. PWM Map Control 4 Register Field Descriptions
          13. 8.6.2.2.13 PWM Frequency Control 1 (PWM_FREQ_CTRL_1) Register (Address = 0x13 [reset = 0x00]
            1. Table 74. PWM Frequency Control 1 Register Field Descriptions
          14. 8.6.2.2.14 PWM Frequency Control 2 (PWM_FREQ_CTRL_2) Register (Address = 0x14 [reset = 0x00]
            1. Table 75. PWM Frequency Control 2 Register Field Descriptions
          15. 8.6.2.2.15 PWM Duty Control Channel 1 (PWM_DUTY_CH1) Register (Address = 0x15) [reset = 0x00]
            1. Table 76. PWM Duty Control Channel 1 Register Field Descriptions
          16. 8.6.2.2.16 PWM Duty Control Channel 2 (PWM_DUTY_CH2) Register (Address = 0x16) [reset = 0x00]
            1. Table 77. PWM Duty Control Channel 2 Register Field Descriptions
          17. 8.6.2.2.17 PWM Duty Control Channel 3 (PWM_DUTY_CH3) Register (Address = 0x17) [reset = 0x00]
            1. Table 78. PWM Duty Control Channel 3 Register Field Descriptions
          18. 8.6.2.2.18 PWM Duty Control Channel 4 (PWM_DUTY_CH4) Register (Address = 0x18) [reset = 0x00]
            1. Table 79. PWM Duty Control Channel 4 Register Field Descriptions
          19. 8.6.2.2.19 PWM Duty Control Channel 5 (PWM_DUTY_CH5) Register (Address = 0x19) [reset = 0x00]
            1. Table 80. PWM Duty Control Channel 5 Register Field Descriptions
          20. 8.6.2.2.20 PWM Duty Control Channel 6 (PWM_DUTY_CH6) Register (Address = 0x1A) [reset = 0x00]
            1. Table 81. PWM Duty Control Channel 6 Register Field Descriptions
          21. 8.6.2.2.21 PWM Duty Control Channel 7 (PWM_DUTY_CH7) Register (Address = 0x1B) [reset = 0x00]
            1. Table 82. PWM Duty Control Channel 7 Register Field Descriptions
          22. 8.6.2.2.22 PWM Duty Control Channel 8 (PWM_DUTY_CH8) Register (Address = 0x1C) [reset = 0x00]
            1. Table 83. PWM Duty Control Channel 8 Register Field Descriptions
          23. 8.6.2.2.23 Slew Rate Control 1 (SR_CTRL_1) Register (Address = 0x1D [reset = 0x00]
            1. Table 84. Slew Rate Control 1 Register Field Descriptions
          24. 8.6.2.2.24 Slew Rate Control 2 (SR_CTRL_2) Register (Address = 0x1E) [reset = 0x00]
            1. Table 85. Slew Rate Control 2 Register Field Descriptions
          25. 8.6.2.2.25 Open-Load Detect (OLD) Control 1 (OLD_CTRL_1) Register (Address = 0x1F) [reset = 0x00]
            1. Table 86. Open-Load Detect (OLD) Control (OLD_CTRL_1) Register Field Descriptions
          26. 8.6.2.2.26 Open-Load Detect (OLD) Control 2 (OLD_CTRL_2) Register (Address = 0x20) [reset = 0x00]
            1. Table 87. Open-Load Detect (OLD) Control (OLD_CTRL_2) Register Field Descriptions
          27. 8.6.2.2.27 Open-Load Detect (OLD) Control 3 (OLD_CTRL_3) Register (Address = 0x21) [reset = 0x00]
            1. Table 88. Open-Load Detect (OLD) Control (OLD_CTRL_3) Register Field Descriptions
          28. 8.6.2.2.28 Open Load Detect (OLD) Control 4 (OLD_CTRL_4) Register (Address = 0x22) [reset = 0x00]
            1. Table 89. Open Load Detect (OLD) Control (OLD_CTRL_4) Register Field Descriptions
          29. 8.6.2.2.29 Open Load Detect (OLD) Control 5 (OLD_CTRL_5) Register (Address = 0x23) [reset = 0x00]
            1. Table 90. Open Load Detect (OLD) Control (OLD_CTRL_5) Register Field Descriptions
          30. 8.6.2.2.30 Open Load Detect (OLD) Control 6 (OLD_CTRL_6) Register (Address = 0x24) [reset = 0x00]
            1. Table 91. Open Load Detect (OLD) Control (OLD_CTRL_6) Register Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Primary Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Motor Current Rating
          2. 9.2.1.2.2 Power Dissipation
      2. 9.2.2 Alternative Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 H-Bridge Requirements for Parallel Operation
      3. 9.2.3 Application Curves
    3. 9.3 Thermal Application
      1. 9.3.1 Power Dissipation
        1. 9.3.1.1 Power Dissipation Due to Device On-State Resistance (RDS(ON))
        2. 9.3.1.2 Power Dissipation Due to Switching Losses
        3. 9.3.1.3 Power Dissipation Due to Quiescent Current
        4. 9.3.1.4 Total Power Dissipation
      2. 9.3.2 PCB Types
      3. 9.3.3 Thermal Parameters
      4. 9.3.4 Transient Thermal
      5. 9.3.5 Device Junction Temperature Estimation
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Electrical Characteristics

at TJ = –40°C to +150°C, VVM = 4.5 to 32 V (Main Supply), VVDD = 3 to 5.5 V (Logic Supply) (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 13.5 V, VVDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VDD, VM)
IVMQ VM sleep mode current VVM = 13.5 V, nSLEEP = 0, TA = 25 °C 0.35 1 µA
VVM = 13.5 V, nSLEEP = 0, TA = 125 °C 2 µA
IVDDQ VDD sleep mode current VVM = 13.5 V, VVDD  = 3.3 V, nSLEEP = 0, TA = 25 °C 0.01 0.3 µA
VVM = 13.5 V, VVDD  = 3.3 V, nSLEEP = 0, TA = 125 °C 2 µA
IVMS VM standby mode current VVM = 13.5 V, nSLEEP = 1, Driver = 'OFF', TA = 25 °C 0.2 0.5 mA
VVM = 13.5 V, nSLEEP = 1, Driver = 'OFF', TA = 125 °C 0.5 mA
IVDDS VDD standby mode current VVM = 13.5 V, VVDD  = 3.3 V, nSLEEP = 1, SPI = 'OFF', TA = 25 °C 0.6 1 mA
VVM = 13.5 V, VVDD  = 3.3 V, nSLEEP = 1, SPI = 'OFF', TA = 125 °C 1 mA
IVM VM operating mode current VVM = 13.5 V, nSLEEP = 1, All High-Side FETs = 'ON', TA = 25 °C 2.6 5 mA
VVM = 13.5 V, nSLEEP = 1, All High-Side FETs = 'ON', TA = 125 °C 5 mA
IVDD VDD operating mode current VVM = 13.5 V, VVDD  = 3.3 V, nSLEEP = 1, All High-Side FETs = 'ON', SPI = 'ON' (5 MHz), TA = 25 °C 2.8 5 mA
VVM = 13.5 V, VVDD  = 3.3 V, nSLEEP = 1, All High-Side FETs = 'ON', SPI = 'ON' (5 MHz), TA = 125 °C 5 mA
tWAKE Wake-up time nSLEEP high to SPI ready 200 µs
tSLEEP Turnoff time nSLEEP low to device sleep 20 µs
LOGIC-LEVEL INPUTS (nSLEEP, SCLK, SDI)
VIL Input logic low voltage 0 0.3*VDD V
VIH Input logic high voltage 0.7*VDD VDD V
VHYS Input logic hysteresis 200 mV
IIL Input logic low current VIN = 0 V –1 1 µA
IIH Input logic high current VIN = VVDD 34 75 µA
CID Input capacitance 15 pF
LOGIC-LEVEL INPUTS (nSCS)
VIL Input logic low voltage 0 0.3*VDD V
VIH Input logic high voltage 0.7*VDD VDD V
VHYS Input logic hysteresis 200 mV
IIL Input logic low current VIN = 0 V 34 75 µA
IIH Input logic high current VIN = VVDD –1 1 µA
CID Input capacitance 15 pF
OPEN-DRAIN OUTPUTS (nFAULT)
VOL Output logic low voltage IOD = 5 mA 0 0.4 V
IOH Output logic high current VOD = 5 V –1 1 µA
COD Output capacitance 15 pF
PUSH-PULL OUTPUTS (SDO)
VOL Output logic low voltage IOP = 5 mA 0 0.4 V
VOH Output logic high voltage IOP = 5 mA VDD–0.6 VDD V
IOL Output logic low current VOP = 0 V –1 1 µA
IOH Output logic high current VOP = VVDD –1 1 µA
COD Output capacitance 30 pF
DRIVER OUTPUTS (OUTx)
RDS(ON) High-side MOSFET on resistance VVM = 13.5 V, IOUT = 0.5 A, TA = 25°C 0.75 1.1 Ω
VVM = 13.5 V, IOUT = 0.5 A, TA = 125°C 1.5 Ω
Low-side MOSFET on resistance VVM = 13.5 V, IOUT = 0.5 A, TA = 25°C 0.75 1.1 Ω
VVM = 13.5 V, IOUT = 0.5 A, TA = 125°C 1.5 Ω
SR Output rise and fall time (high-side and low-side) VVM = 13.5 V, 10-90%, RLOAD = 27 Ω, HBx_SR = 0b 0.6 V/µs
VVM = 13.5 V, 10-90%, RLOAD = 27 Ω, HBx_SR = 1b 2.5 V/µs
tDEAD Output dead time (high to low / low to high) VVM = 13.5 V, SR = 0, HS/LS driver OFF to LS/HS driver ON 8 20 32 µs
VVM = 13.5 V, SR = 1, HS/LS driver OFF to LS/HS driver ON 2 5 15 µs
tPD Propagation delay (high-side / low-side ON/OFF) High-side ON (SPI last transition) to OUTx transition, SR = 0 5 12 25 µs
High-side ON (SPI last transition) to OUTx transition, SR = 1 3 5 10 µs
ILEAK Leakage current low-side VOUTx = 13.5 V, nSLEEP = 1, SR = 0b 6 10 µA
VOUTx = 13.5 V, nSLEEP = 1, SR = 1b 20 35 µA
VOUTx = 13.5 V, nSLEEP = 0 4 15 µA
Leakage current high-side VOUTx = 0 V, nSLEEP = 1 2 µA
VOUTx = 0 V, nSLEEP = 0 2 µA
PWM MODE
fPWM PWM switching frequency PWM_CHx_FREQ = 00b 80 Hz
PWM_CHx_FREQ = 01b 100 Hz
PWM_CHx_FREQ = 10b 200 Hz
PWM_CHx_FREQ = 11b 2000 Hz
PROTECTION CIRCUITS
VUVLO Supply undervoltage lockout (UVLO) Supply rising 4.0 4.5 V
Supply falling 3.8 4.3 V
VUVLO_HYS Supply undervoltage lockout hysteresis Rising to falling theshold 200 mV
tUVLO Supply undervoltage deglitch time 10   µs
VOVP Supply overvoltage protection (OVP) Supply rising, EXT_OVP = 0b 21 25 V
Supply falling, EXT_OVP = 0b 20 24 V
Supply rising, EXT_OVP = 1b 32.7 35 V
Supply falling, EXT_OVP = 1b 32 34.3 V
VOVP_HYS Supply overvoltage protection hysteresis Rising to falling theshold, EXT_OVP = 0b 1 V
Rising to falling theshold, EXT_OVP = 1b 0.7 V
tOVP Supply overvoltage deglitch time 10 µs
VPOR Logic undervoltage (POR) Supply rising 2.45 3 V
Supply falling 2.4 2.95 V
VPOR_HYS Logic undervoltage hysteresis Rising to falling theshold 75 mV
IOCP Overcurrent protection trip point(1)(2) 1.3 1.8 2.3 A
tOCP Overcurrent protection deglitch time OCP_DEG = 000b 10 µs
OCP_DEG = 001b 5 µs
OCP_DEG = 010b 2.5 µs
OCP_DEG = 011b 1 µs
OCP_DEG = 100b 60 µs
OCP_DEG = 101b 40 µs
OCP_DEG = 110b 30 µs
OCP_DEG = 111b 20 µs
IOLD Open load detection current Current flowing from VM to OUTx (High-Side = ON) or OUTx to GND (Low-Side = ON) 2 9 18 mA
IOLD_NEG Negative open load detection current Current flowing from OUTx to VM (High-Side = ON) or GND to OUTx (Low-Side = ON) 2 15 30 mA
IOLD_LOW Open load detection current in low current OLD mode Current flowing from VM to OUTx (High-Side = ON) or OUTx to GND (Low-Side = ON) 0.2 0.8 2 mA
IOL_GND Passive OLD current DRV8908/6/4, FETs in Hi-Z state, current from OUTx to GND during OLD trip 100 µA
VOL_GND Passive OLD voltage threshold DRV8908/6/4, FETs in Hi-Z state, voltage at OUTx during OLD trip for GND-connected load 3.1 V
IOL_VM Passive OLD current DRV8908/6/4, FETs in Hi-Z state, current from VM to OUTx for OLD trip, HBX_VM_POLD = 0b 100 µA
VOL_VM Passive OLD voltage threshold DRV8908/6/4, FETs in Hi-Z state, voltage at OUTx during OLD trip for VM-connected load, HBX_VM_POLD = 0b 1.1 V
IOL_VM Passive OLD current DRV8908/6/4, FETs in Hi-Z state, current from VM to OUTx for OLD trip, HBX_VM_POLD = 1b 480 µA
VOL_VM Passive OLD voltage threshold DRV8908/6/4, FETs in Hi-Z state, voltage at OUTx during OLD trip for VM connceted load, HBX_VM_POLD = 1b 1.6 V
ROL Passive OLD detect resistance threshold DRV8908/6/4, FETs in Hi-Z state, Full bridge connection 5 100 kΩ
ROL Passive OLD detect resistance threshold DRV8908/6/4, FETs in Hi-Z State, Load connected to GND 5 100 kΩ
ROL Passive OLD detect resistance threshold DRV8908/6/4, FETs in Hi-Z State, Load connected to VM, HBX_VM_POLD = 0b 5 400 kΩ
ROL Passive OLD detect resistance threshold DRV8908/6/4, FETs in Hi-Z State, Load connected to VM, HBX_VM_POLD = 1b 5 100 kΩ
tOLD Open load deglitch time Active OLD (Continuous Mode) 2 3 4 ms
tOLD Open load deglitch time Active OLD (PWM Mode) 150 200 300 µs
TOTW Thermal warning temperature Die temperature (Tj) 120 140 170 °C
TOTW_HYS Thermal warning hysteresis Die temperature (Tj) 20 °C
TOTSD Thermal shutdown temperature Die temperature (Tj) 150 175 200 °C
TOTSD_HYS Thermal shutdown hysteresis Die temperature (Tj) 20 °C
For 20-V < VVM < 28-V, the OCP deglicth time must be limited to 10-µs (Default Deglitch Value, OCP_DEG = 000b).
For VVM > 28 V, the OCP deglicth time must be limited to 1-µs (Lowest Deglitch Value, OCP_DEG = 011b).