ZHCSIO5B October   2017  – January 2021 DRV8873-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
        1. 7.3.1.1 Control Modes
        2. 7.3.1.2 Half-Bridge Operation
        3. 7.3.1.3 22
        4. 7.3.1.4 Internal Current Sense and Current Regulation
        5. 7.3.1.5 Slew-Rate Control
        6. 7.3.1.6 Dead Time
        7. 7.3.1.7 Propagation Delay
        8. 7.3.1.8 nFAULT Pin
        9. 7.3.1.9 nSLEEP as SDO Reference
      2. 7.3.2 Motor Driver Protection Circuits
        1. 7.3.2.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.2.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.2.3 Overcurrent Protection (OCP)
          1. 7.3.2.3.1 Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.2.3.2 Automatic Retry (OCP_MODE = 01b)
          3. 7.3.2.3.3 Report Only (OCP_MODE = 10b)
          4. 7.3.2.3.4 Disabled (OCP_MODE = 11b)
        4. 7.3.2.4 Open-Load Detection (OLD)
          1. 7.3.2.4.1 Open-Load Detection in Passive Mode (OLP)
          2. 7.3.2.4.2 Open-Load Detection in Active Mode (OLA)
        5. 7.3.2.5 Thermal Shutdown (TSD)
          1. 7.3.2.5.1 Latched Shutdown (TSD_MODE = 0b)
          2. 7.3.2.5.2 Automatic Recovery (TSD_MODE = 1b)
        6. 7.3.2.6 Thermal Warning (OTW)
      3. 7.3.3 Hardware Interface
        1. 7.3.3.1 MODE (Tri-Level Input)
        2. 7.3.3.2 Slew Rate
    4. 7.4 Device Functional Modes
      1. 7.4.1 Motor Driver Functional Modes
        1. 7.4.1.1 Sleep Mode (nSLEEP = 0)
        2. 7.4.1.2 Disable Mode (nSLEEP = 1, DISABLE = 1)
        3. 7.4.1.3 Operating Mode (nSLEEP = 1, DISABLE = 0)
        4. 7.4.1.4 nSLEEP Reset Pulse
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI) Communication
        1. 7.5.1.1 SPI Format
        2. 7.5.1.2 SPI for a Single Slave Device
        3. 7.5.1.3 SPI for Multiple Slave Devices in Parallel Configuration
        4. 7.5.1.4 SPI for Multiple Slave Devices in Daisy Chain Configuration
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Motor Voltage
        2. 8.2.1.2 Drive Current and Power Dissipation
        3. 8.2.1.3 Sense Resistor
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Thermal Considerations
        2. 8.2.2.2 Heatsinking
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.6 Register Maps

Table 7-18 lists the memory-mapped registers for the device. All register addresses not listed in Table 7-18 should be considered as reserved locations and the register contents should not be modified.

Table 7-18 Memory Map
Register
Name		76543210Access
Type		Address
FAULT StatusRSVDFAULTOTWUVLOCPUVOCPTSDOLDR0x00
DIAG StatusOL1OL2ITRIP1ITRIP2OCP_H1OCP_L1OCP_H2OCP_L2R0x01
IC1 ControlTOFFSPI_INSRMODERW0x02
IC2 ControlITRIP_REPTSD_MODEOTW_REPDIS_CPUVOCP_TRETRYOCP_MODERW0x03
IC3 ControlCLR_FLTLOCKOUT1_DISOUT2_DISEN_IN1PH_IN2RW0x04
IC4 ControlRSVDEN_OLPOLP_DLYEN_OLAITRIP_LVLDIS_ITRIPRW0x05

Complex bit access types are encoded to fit into small table cells. Table 7-19 shows the codes that are used for access types in this section.

Table 7-19 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.1 Status Registers

The status registers are used to reporting warning and fault conditions. Status registers are read-only registers

Table 7-20 lists the memory-mapped registers for the status registers. All register offset addresses not listed in Table 7-20 should be considered as reserved locations and the register contents should not be modified.

Table 7-20 Status Registers Summary Table
AddressRegister NameSection
0x00FAULT statusGo
0x01DIAG statusGo

7.6.2 FAULT Status Register Name (address = 0x00)

FAULT status is shown in Figure 7-23 and described in Table 7-21.

Read-only

Figure 7-23 FAULT Status Register
76543210
RSVDFAULTOTWUVLOCPUVOCPTSDOLD
R-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-21 FAULT Status Register Field Descriptions
BitFieldTypeDefaultDescription
7RSVDR0b

Reserved

6FAULTR0b

Global FAULT status register. Compliments the nFAULT pin

5OTWR0b

Indicates overtemperature warning

4UVLOR0b

Indicates UVLO fault condition

3CPUVR0b

Indicates charge-pump undervoltage fault condition

2OCPR0b

Indicates an overcurrent condition

1TSDR0b

Indicates an overtemperature shutdown

0OLDR0b

Indicates an open-load detection

7.6.3 DIAG Status Register Name (address = 0x01)

DIAG status is shown in Figure 7-24 and described in Table 7-22.

Read-only

Figure 7-24 DIAG Status Register
76543210
OL1OL2ITRIP1ITRIP2OCP_H1OCP_L1OCP_H2OCP_L2
R-0bR-0bR-0bR-0bR-0bR-0bR-0bR-0b
Table 7-22 DIAG Status Register Field Descriptions
BitFieldTypeDefaultDescription
7OL1R0b

Indicates open-load detection on half bridge 1

6OL2R0b

Indicates open-load detection on half bridge 2

5ITRIP1R0b

Indicates the current regulation status of half bridge 1.

0b = Indicates output 1 is not in current regulation

1b = Indicates output 1 is in current regulation

4ITRIP2R0b

Indicates the current regulation status of half bridge 2.

0b = Indicates output 2 is not in current regulation

1b = Indicates output 2 is in current regulation

3OCP_H1R0b

Indicates overcurrent fault on the high-side FET of half bridge 1

2OCP_L1R0b

Indicates overcurrent fault on the low-side FET of half bridge 1

1OCP_H2R0b

Indicates overcurrent fault on the high-side FET of half bridge 2

0OCP_L2R0b

Indicates overcurrent fault on the low-side FET of half bridge 2

7.6.4 Control Registers

The IC control registers are used to configure the device. Status registers are read and write capable.

Table 7-23 lists the memory-mapped registers for the control registers. All register offset addresses not listed in Table 7-23 should be considered as reserved locations and the register contents should not be modified.

Table 7-23 Control Registers Summary Table
AddressRegister NameSection
0x02IC1 controlGo
0x03IC2 controlGo
0x04IC3 controlGo
0x05IC4 controlGo

7.6.5 IC1 Control Register (address = 0x02)

IC1 control is shown in Figure 7-25 and described in Table 7-24.

Read/Write

Figure 7-25 IC1 Control Register
76543210
TOFFSPI_INSRMODE
R/W-01bR/W-0bR/W-100bR/W-01b
Table 7-24 IC1 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7-6TOFFR/W01b

00b = 20 µs

01b = 40 µs

10b = 60 µs

11b = 80 µs

5SPI_INR/W0b

0b = Outputs follow input pins (INx)

1b = Outputs follow SPI registers EN_IN1 and PH_IN2

4-2SRR/W100b

000b = 53.2-V/µs rise time

001b = 34-V/µs rise time

010b = 18.3-V/µs rise time

011b = 13-V/µs rise time

100b = 10.8-V/µs rise time

101b = 7.9-V/µs rise time

110b = 5.3-V/µs rise time

111b = 2.6-V/µs rise time

1-0MODER/W01b

00b = PH/EN

01b = PWM

10b = Independent half bridge

11b = Input disabled; bridge Hi-Z

7.6.6 IC2 Control Register (address = 0x03)

IC2 control is shown in Figure 7-26 and described in Table 7-25.

Read/Write

Figure 7-26 IC2 Control Register
76543210
ITRIP_REPTSD_MODEOTW_REPDIS_CPUVOCP_TRETRYOCP_MODE
R/W-0bR/W-0bR/W-0bR/W-0bR/W-11bR/W-00b
Table 7-25 IC2 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7ITRIP_REPR/W0b

0b = ITRIP is not reported on nFAULT or the FAULT bit

1b = ITRIP is reported on nFAULT and the FAULT bit

6TSD_MODER/W0b

0b = Overtemperature condition causes a latched fault

1b = Overtemperature condition causes an automatic recovery fault

5OTW_REPR/W0b

0b = OTW is not reported on nFAULT or the FAULT bit

1b = OTW is reported on nFAULT and the FAULT bit

4DIS_CPUVR/W0b

0b = Charge pump undervoltage fault is enabled

1b = Charge pump undervoltage fault is disabled

3-2OCP_TRETRYR/W11b

00b = Overcurrent retry time is 0.5 ms

01b = Overcurrent retry time is 1 ms

10b = Overcurrent retry time is 2 ms

11b = Overcurrent retry time is 4 ms

1-0OCP_MODER/W00b

00b = Overcurrent condition causes a latched fault

01b = Overcurrent condition causes an automatic retrying fault

10b = Overcurrent condition is report only but no action is taken

11b = Overcurrent condition is not reported and no action is taken

7.6.7 IC3 Control Register (address = 0x04)

IC3 control is shown in Figure 7-27 and described in Table 7-26.

Read/Write

Figure 7-27 IC3 Control Register
76543210
CLR_FLTLOCKOUT1_DISOUT2_DISEN_IN1PH_IN2
R/W-0bR/W-100bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-26 IC3 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7CLR_FLTR/W0b

Write a 1b to this bit to clear the fault bits. This bit is automatically reset after a write.

6-4LOCKR/W100b

Write 011b to this register to lock all register settings in the IC1 control register except to these bits and address 0x04, bit 7 (CLR_FLT)
Write 100b to this register to unlock all register settings in the IC1 control register

3OUT1_DISR/W0b

Enabled only in the Independent PWM mode

0b = Half bridge 1 enabled

1b = Half bridge 1 disabled (Hi-Z)

2OUT2_DISR/W0b

Enabled only in the Independent PWM mode

0b = Half bridge 2 enabled

1b = Half bridge 2 disabled (Hi-Z)

1EN_IN1R/W0b

EN/IN1 bit to control the outputs through SPI (when SPI_IN = 1b)

0PH_IN2R/W0b

PH/IN2 bit to control the outputs through SPI (when SPI_IN = 1b)

7.6.8 IC4 Control Register (address = 0x05)

IC4 control is shown in Figure 7-28 and described in Table 7-27.

Read/Write

Figure 7-28 IC4 Control Register
76543210
RSVDEN_OLPOLP_DLYEN_OLAITRIP_LVLDIS_ITRIP
R/W-0bR/W-0bR/W-0bR/W-0bR/W-10bR/W-00b
Table 7-27 IC4 Control Register Field Descriptions
BitFieldTypeDefaultDescription
7RSVDR/W0b

Reserved

6EN_OLPR/W0b

Write 1b to run open load diagnostic in standby mode. When open load test is complete EN_OLP returns to 0b (status check)

5OLP_DLYR/W0b

0b = Open load diagnostic delay is 300 µs

1b = Open load diagnostic delay is 1.2 ms

4EN_OLAR/W0b

0b = Open load diagnostic in active mode is disabled

1b = Enable open load diagnostics in active mode

3-2ITRIP_LVLR/W10b

00b = 4 A

01b = 5.4 A

10b = 6.5 A

11b = 7 A

1-0DIS_ITRIPR/W00b

00b = Current regulation is enabled

01b = Current regulation is disabled for OUT1

10b = Current regulation is disabled for OUT2

11b = Current regulation is disabled for both OUT1 and OUT2