SLVSBN4C January 2013 – August 2016 DRV8839
The DRV8839 is an integrated motor driver solution used for brushed motor control. The device integrates two independent ½ H-bridge, and can drive one motor in both directions or two motors in one direction. The output driver block for each ½ H-bridge consists of N-channel power MOSFETs. An internal charge pump generates the gate drive voltages. Protection features include overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature protection.
The DRV8839 allows separation of the motor voltage and logic voltage if desired. If VM and VCC are less than
7 V, the two voltages may be connected.
The control interface of the DRV8839 uses INx and ENx to control each ½ H-bridge separately.
The DRV8839 is fully protected against undervoltage, overcurrent, and overtemperature events.
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge disables. After approximately 1 ms, the bridge will be re-enabled automatically.
Overcurrent conditions on both high-side and low-side devices; a short to ground, supply, or across the motor winding result in an overcurrent shutdown.
If the die temperature exceeds safe limits, all FETs in the H-bridge disables. Operation automatically resumes once the die temperature has fallen to a safe level.
If at any time the voltage on the VCC pin falls below the undervoltage lockout threshold voltage, all circuitry in the device disables and internal logic resets. Operation resumes when VCC rises above the UVLO threshold.
|FAULT||CONDITION||ERROR REPORT||H-BRIDGE||INTERNAL CIRCUITS||RECOVERY|
|VCC undervoltage (UVLO)||VCC < VUVLO||None||Disabled||Disabled||VCC > VUVLO|
|Overcurrent (OCP)||IOUT > IOCP||None||Disabled||Operating||tOCR|
|Thermal shutdown (TSD)||TJ > TTSD||None||Disabled||Operating||TJ < TTSD – THYS|
The DRV8839 is active when the nSLEEP pin is set to a logic high. When in sleep mode, the ½ H-bridge FETs are disabled (High-Z).
|OPERATING MODE||CONDITION||H-BRIDGE||INTERNAL CIRCUITS|
|Sleep mode||nSLEEP low||Disabled||Disabled|
|Fault encountered||Any fault condition met||Disabled||See Table 1|
The DRV8839 is controlled using separate enable and input pins for each ½-H-bridge.
The following table shows the logic for the DRV8839:
If the nSLEEP pin reaches a logic-low state, the DRV8839 enters a low-power sleep mode. In this state all unnecessary internal circuitry powers down.
If a single DC motor connects to the DRV8839, it is connected between the OUT1 and OUT2 pins as shown in Figure 7:
Motor operation is controlled as show in Table 4.
|0||X||X||X||Z||See (1)||Off (coast)|
|X||0||X||X||See (2)||Z||Off (coast)|
Two DC motors can be connected to the DRV8839. In this mode, it is not possible to reverse the direction of the motors; they turn only in one direction. The connections are shown in Figure 8:
Motor operation is controlled shown in Table 5.