ZHCS016E January 2011 – July 2015 DRV8833
The DRV8833 device is an integrated motor driver solution for brushed DC or bipolar stepper motors. The device integrates two NMOS H-bridges and current regulation circuitry. The DRV8833 can be powered with a supply voltage from 2.7 to 10.8 V and can provide an output current up to 1.5-A RMS.
A simple PWM interface allows easy interfacing to the controller circuit.
The current regulation is a fixed frequency PWM slow decay.
The device includes a low-power sleep mode, which lets the system save power when not driving the motor.
DRV8833 contains two identical H-bridge motor drivers with current-control PWM circuitry. Figure 5 shows a block diagram of the circuitry.
The AIN1 and AIN2 input pins control the state of the AOUT1 and AOUT2 outputs; similarly, the BIN1 and BIN2 input pins control the state of the BOUT1 and BOUT2 outputs. Table 1 shows the logic.
The inputs can also be used for PWM control of the motor speed. When controlling a winding with PWM, when the drive current is interrupted, the inductive nature of the motor requires that the current must continue to flow. This is called recirculation current. To handle this recirculation current, the H-bridge can operate in two different states: fast decay or slow decay. In fast decay mode, the H-bridge is disabled and recirculation current flows through the body diodes; in slow decay, the motor winding is shorted.
To PWM using fast decay, the PWM signal is applied to one xIN pin while the other is held low; to use slow decay, one xIN pin is held high.
|PWM||0||Forward PWM, fast decay|
|1||PWM||Forward PWM, slow decay|
|0||PWM||Reverse PWM, fast decay|
|PWM||1||Reverse PWM, slow decay|
Figure 6 shows the current paths in different drive and decay modes.
The current through the motor windings may be limited, or controlled, by a fixed-frequency PWM current regulation, or current chopping. For DC motors, current control is used to limit the start-up and stall current of the motor. For stepper motors, current control is often used at all times.
When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding. If the current reaches the current chopping threshold, the bridge disables the current until the beginning of the next PWM cycle. Immediately after the current is enabled, the voltage on the xISEN pin is ignored for a fixed period of time before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. This blanking time also sets the minimum on time of the PWM when operating in current chopping mode.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISEN pins with a reference voltage. The reference voltage is fixed at 200 mV.
The chopping current is calculated in Equation 1.
Example: If a 1-Ω sense resistor is used, the chopping current will be 200 mV/1 Ω = 200 mA.
Once the chopping current threshold is reached, the H-bridge switches to slow decay mode. Winding current is recirculated by enabling both of the low-side FETs in the bridge. This state is held until the beginning of the next fixed-frequency PWM cycle.
If current control is not needed, the xISEN pins should be connected directly to ground.
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the gate drive charge pump is stopped, all internal logic is reset, and all internal clocks are stopped. All inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time (up to 1 ms) needs to pass before the motor driver becomes fully operational. To make the board design simple, the nSLEEP can be pulled up to the supply (VM). TI recommends using a pullup resistor when this is done. This resistor limits the current to the input in case VM is higher than 6.5 V. Internally, the nSLEEP pin has a 500-kΩ resistor to GND. It also has a clamping Zener diode that clamps the voltage at the pin at 6.5 V. Currents greater than 250 µA can cause damage to the input structure. Hence the recommended pullup resistor would be between 20 kΩ and
The DRV8833 is fully protected against undervoltage, overcurrent and overtemperature events.
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive. If this analog current limit persists for longer than the OCP deglitch time, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. The driver will be re-enabled after the OCP retry period (tOCP) has passed. nFAULT becomes high again at this time. If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and nFAULT remains deasserted. Please note that only the H-bridge in which the OCP is detected will be disabled while the other bridge will function normally.
Overcurrent conditions are detected independently on both high- and low-side devices; that is, a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for PWM current control, so it functions even without presence of the xISEN resistors.
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be driven low. Once the die temperature has fallen to a safe level, operation will automatically resume.
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled, and all internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. nFAULT is driven low in the event of an undervoltage condition.
|FAULT||CONDITION||ERROR REPORT||H-BRIDGE||INTERNAL CIRCUITS||RECOVERY|
|VM undervoltage (UVLO)||VM < 2.5 V||None||Disabled||Disabled||VM > 2.7 V|
|Overcurrent (OCP)||IOUT > IOCP||FAULTn||Disabled||Operating||OCP|
|Thermal Shutdown (TSD)||TJ > TTSD||FAULTn||Disabled||Operating||TJ < TTSD – THYS|
The DRV8833 is active unless the nSLEEP pin is brought logic low. In sleep mode, the H-bridge FETs are disabled (Hi-Z). The DRV8833 is brought out of sleep mode automatically if nSLEEP is brought logic high. tWAKE must elapse before the outputs change state after wakeup.
|Operating||nSLEEP pin high||Operating||Operating|
|Sleep mode||nSLEEP pin low||Disabled||Disabled|
|Fault encountered||Any fault condition met||Disabled||See Table 3|