Bootstrap Capacitor and GVDD Capacitor Selection

The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for normal operation. Equation 2 calculates the maximum allowable voltage drop across the bootstrap capacitor:

Equation 2.

= 12 V – 0.85 V – 4.5 V = 6.65 V

where

• V_GVDD is the supply voltage of the gate drive
• V_BOOTD is the forward voltage drop of the bootstrap diode
• V_BSTUV is the threshold of the bootstrap undervoltage lockout

In this example the allowed voltage drop across bootstrap capacitor is 6.65 V. It is generally recommended that ripple voltage on both the bootstrap capacitor and GVDD capacitor should be minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value between 0.5 V to 1 V.

The total charge needed per switching cycle can be estimated with Equation 3:

Equation 3.

= 48 nC + 220 μA/20 kHz = 50 nC + 11 nC = 59 nC

where

• Q_G is the total MOSFET gate charge
• I_{LBS_TRAN} is the bootstrap pin leakage current
• f_SW is the is the PWM frequency

The minimum bootstrap capacitor an then be estimated as below assuming 1-V ΔV_BSTx:

Equation 4.

= 59 nC / 1 V = 59 nF

The calculated value of minimum bootstrap capacitor is 59 nF. It should be noted that, this value of capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than calculated value to allow for situations where the power stage may skip pulse due to various transient conditions. It is recommended to use a 100 nF bootstrap capacitor in this example. It is also recommended to include enough margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.

Equation 5.

= 10*100 nF = 1 μF

For this example application, choose 1-µF C_GVDD capacitor. Choose a capacitor with a voltage rating at least twice the maximum voltage that it will be exposed to because most ceramic capacitors lose significant capacitance when biased. This value also improves the long term reliability of the system.

Gate Resistance Selection

The slew rate of the SHx connection will be dependent on the rate at which the gate of the external MOSFETs is controlled. The pull-up/pull-down strength of the DRV8770 is fixed internally, hence slew rate of gate voltage can be controlled with an external series gate resistor. In some applications the gate charge, which is load on gate driver device, is significantly larger than gate driver peak output current capability. In such applications external gate resistors can limit the peak output current of the gate driver. External gate resistors are also used to damp ringing and noise.

The specific parameters of the MOSFET, system voltage, and board parasitics will all affect the final slew rate, so generally selecting an optimal value or configuration of external gate resistor is an iterative process.