7.3.1 PWM Motor Drivers

The DRV8704 contains two H-bridge motor gate drivers with current-control PWM circuitry.

7.3.2 Direct PWM Input Mode (Dual Brushed DC Gate Driver)

In direct PWM input mode, the AIN1, AIN2, BIN1, and BIN2 directly control the state of the output drivers. This allows for driving up to two brushed DC motors. Table 1 shows the logic.

In direct PWM mode, the current control circuitry is still active. The full-scale VREF is set to 2.75 V. The TORQUE register may be used to scale this value, and the ISEN sense amplifier gain may still be set using the ISGAIN bits of the CTRL register.

Figure 8. Motor Driver Block Diagram

7.3.3 Current Regulation

The current through the motor windings is regulated by an adjustable fixed-off-time PWM current regulation circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage and inductance of the winding and the magnitude of the back EMF present. Once the current hits the current chopping threshold, the bridge disables the current for a fixed period of time, which is programmable between 525 ns and 128 µs by writing to the TOFF bits in the OFF register. After the off time expires, the bridge is re-enabled, starting another PWM cycle.

Note that the decay mode is set by DECMOD bits in the DECAY register. Slow, fast, mixed, or auto mixed decay modes are available.

The chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xISENx pins, multiplied by the gain of the current sense amplifier, with a reference voltage. The current sense amplifier is programmable in the CTRL register.

When driving in PWM mode, the chopping current is calculated as follows:

Equation 1.

where

• TORQUE is the setting of the TORQUE bits
• ISGAIN is the programmed gain of the ISENSE amplifiers (5, 10, 20, or 40).

7.3.4 Decay Modes

During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM current chopping threshold is reached. This is shown in the diagram below as case 1. The current flow direction shown indicates positive current flow in the step table below.

Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay.

In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. If the winding current approaches zero, the bridge is disabled to prevent any reverse current flow. Fast decay mode is shown in the diagram below as case 2.

In slow decay mode, winding current is recirculated by enabling both of the low-side FETs in the bridge. This is shown as case 3 in Figure 9.

Figure 9. Decay Mode Current

Figure 10. Decay Mode Comparison

The DRV8704 supports fast decay and slow decay modes. In addition it supports fixed mixed decay and auto mixed decay modes. Decay mode is selected by the DECMOD bits in the DECAY register.

Mixed decay mode begins as fast decay, but after a programmable period of time (set by the TDECAY bits in the DECAY register) switches to slow decay mode for the remainder of the fixed off time.

Auto mixed decay mode samples the current level at the end of the blanking time, and if the current is above the Itrip threshold, immediately changes the H-bridge to fast decay. During fast decay, the (negative) current is monitored, and when it falls below the Itrip threshold (and another blanking time has passed), the bridge is switched to slow decay. Once the fixed off time expires, a new cycle is started.

If the bridge is turned on and at the end of t_BLANK the current is below the Itrip threshold, the bridge remains on until the current reaches Itrip. Then slow decay is entered for the fixed off time, and a new cycle begins.

Refer to Figure 11.

The upper waveform shows the behavior if I < Itrip at the end of t_BLANK. This is a stable, slow decay mode of operation.

The lower waveform shows what happens when I > Itrip at the end of t_BLANK. Note that (at slow motor speeds, where back EMF is not significant), the current increase during the ON phase is the same magnitude as the current decrease in fast decay, since both times are controlled by t_BLANK, and the rate of change is the same (full VM is applied to the load inductance in both cases, but in opposite directions). In this case, the current will gradually be driven down until the peak current is just hitting Itrip at the end of the blanking time, after which some cycles will be slow decay, and some will be mixed decay.

Figure 11. Auto Mixed Decay

To accurately detect zero current, an internal offset has been intentionally placed in the zero current detection circuit. If an external filter is placed on the current sense resistor to the xISENN and xISENP pins, symmetry must be maintained. This means that any resistance between the bottom of the R_ISENSE resistor and xISENN must be matched by the same resistor value (1% tolerance) between the top of the R_ISENSE resistor and xISENP. Ensure a maximum resistance of 500 Ω. The capacitor value should be chosen such that the RC time constant is between 50 and 60 ns. Any external filtering on these pins is optional and not required for operation.

Figure 12. Optional Filtering for Sense Amplifiers

7.3.5 Blanking Time

After the current is enabled in an H-bridge, the voltage on the ISEN pin is ignored for a period of time before enabling the current sense circuitry. This blanking time is adjustable from 500 ns to 5.14 µs, in 20-ns increments, by setting the TBLANK bits in the BLANK register. Note that the blanking time also sets the minimum drive time of the PWM.

The same blanking time is applied to the fast decay period in auto mixed decay mode. The PWM will ignore any transitions on Itrip after entering fast decay mode, until the blanking time has expired.

7.3.6 Gate Drivers

An internal charge pump circuit and pre-drivers inside the DRV8704 directly drive N-channel MOSFETs, which drive the motor current.

The peak drive current of the pre-drivers is adjustable by setting the bits in the DRIVE register. Peak source currents may be set to 50 mA, 100 mA, 150 mA, or 200 mA. The peak sink current is approximately 2× the peak source current. Adjusting the peak current will change the output slew rate, which also depends on the FET input capacitance and gate charge.

When changing the state of the output, the peak current is applied for a short period of time (t_DRIVE), to charge the gate capacitance. After this time, a weak current source is used to keep the gate at the desired state. When selecting the gate drive strength for a given external FET, the selected current must be high enough to fully charge and discharge the gate during the time when driven at full current, or excessive power will be dissipated in the FET.

During high-side turn-on, the low-side gate is pulled low. This prevents the gate-drain capacitance of the low-side FET from inducing turn-on.

The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and low-side FETs from conducting at the same time. Additional dead time is added with digital delays. This delay can be selected by setting the DTIME bits in the CTRL register.

Figure 13. Gate Driver

Figure 14. Gate Driver Source Capability

Figure 15. Gate Driver Sink Capability

7.3.7 Configuring Gate Drivers

IDRIVE and TDRIVE are selected based on the size of external FETs used. These registers need to be configured so that the FET gates are charged completely during TDRIVE. If IDRIVE and TDRIVE are chosen to be too low for a given FET, then the FET may not turn on completely. It is suggested to adjust these values in-system with the required external FETs and motors in order to determine the best possible setting for any application.

Note that TDRIVE will not increase the PWM time or change the PWM chopping frequency.

In a system with capacitor charge Q and desired rise time RT, IDRIVE, and TDRIVE can be initially selected based on:

Equation 2.

For best results, select the smallest IDRIVE and TDRIVE that meet the above conditions.

Example:

If the gate charge is 15 nC and the desired rise time is 400 ns, then select

IDRIVEP = 50 mA, IDRIVEN = 100 mA

TDRIVEP = TDRIVEN = 1050 ns

7.3.8 External FET Selection

In a typical setup, the DRV8704 can support external FETs over 50 nC each. However, this capacity can be lower or higher based on the device operation. For an accurate calculation of FET driving capacity, use Equation 4.

Equation 4.

Example:

If a DTIME is set to 0 (410 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0 (525 ns), then the DRV8704 will support Q < 11.5 nC FETs. (Please note that this is an absolute worst-case scenario with a PWM frequency about 430 kHz)

If a DTIME is set to 0 (410 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x14 (10 µs), then the DRV8704 will support Q < 59 nC FETs (PWM frequency about 85 kHz).

If a DTIME is set to 0 (410 ns), TBLANK is set to 0 (1 µs), and TOFF is set to 0x60 (48 µs), then the DRV8704 will support Q < 249 nC FETs (PWM frequency about 20 kHz).

7.3.9 Protection Circuits

The DRV8704 is fully protected against undervoltage, overcurrent, and overtemperature events.

7.3.10 Serial Data Format

The serial data consists of a 16-bit serial write, with a read/write bit, 3 address bits and 12 data bits. The three address bits identify one of the registers defined in the register section above. To complete the read or write transaction, SCS must be set to a logic 0.

To write to a register, data is shifted in after the address as shown in the timing diagram below. The first bit at the beginning of the access must be logic low for a write operation.

Figure 16. Serial Write Operation

Data may be read from the registers through the SDATO pin. During a read operation, only the address is used form the SDATI pin; the data bits following are ignored. The first bit at the beginning of the access must be logic high for a read operation.

1. Any amount of time may pass between bits, as long as SCS stays active high. This allows two 8-bit writes to be used

Figure 17. Serial Read Operation

Table 2. Functional Modes

7.5.1 Control Registers

The DRV8704 uses internal registers to control the operation of the motor. The registers are programmed by a serial SPI communications interface. At power-up or reset, the registers will be pre-loaded with default values as shown in Table 3.

Following is a map of the DRV8704 registers:

Individual register contents are defined in the following sections.