ZHCSEB6 October   2015 DRV8704

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode (Dual Brushed DC Gate Driver)
      3. 7.3.3  Current Regulation
      4. 7.3.4  Decay Modes
      5. 7.3.5  Blanking Time
      6. 7.3.6  Gate Drivers
      7. 7.3.7  Configuring Gate Drivers
      8. 7.3.8  External FET Selection
      9. 7.3.9  Protection Circuits
        1. 7.3.9.1 Overcurrent Protection (OCP)
        2. 7.3.9.2 Gate Driver Fault (PDF)
        3. 7.3.9.3 Thermal Shutdown (TSD)
        4. 7.3.9.4 Undervoltage Lockout (UVLO)
      10. 7.3.10 Serial Data Format
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1 Control Registers
        1. 7.5.1.1 CTRL Register (Address = 0x00h)
        2. 7.5.1.2 TORQUE Register (Address = 0x01h)
        3. 7.5.1.3 OFF Register (Address = 0x02h)
        4. 7.5.1.4 BLANK Register (Address = 0x03h)
        5. 7.5.1.5 DECAY Register (Address = 0x04h)
        6. 7.5.1.6 Reserved Register Address = 0x05h
        7. 7.5.1.7 DRIVE Register Address = 0x06h
        8. 7.5.1.8 STATUS Register (Address = 0x07h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 Current Chopping Configuration
        4. 8.2.2.4 Decay Modes
        5. 8.2.2.5 Sense Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

The VM terminal should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.01 μF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace or ground plane connection to the device GND pin.

The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an electrolytic. The bulk capacitor should be placed to minimize the distance of the high-current path through the external FETs. The connecting metal trace widths should be as wide as possible, and numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.

A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.1 μF rated for VM is recommended. Place this component as close to the pins as possible.

A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 1 μF rated for 16 V is recommended. Place this component as close to the pins as possible.

Bypass VINT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin as possible.

Bypass V5 to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the pin as possible.

If desired, align the external NMOS FETs as shown on the next page to facilitate layout. Route the AOUT1, AOUT2, BOUT1, and BOUT2 nets to the motor windings.

Use separate traces to connect the xISENP and xISENN pins to the sense resistor terminals.

10.2 Layout Example

DRV8704 layout_ex_lvsd29.gif Figure 22. Board Layout Example