ZHCSI91B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
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After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time elapses. The FAULT, SEN_OCP, and sense OCP bits remain latched until the tRETRY period expires.