ZHCSIC7H 数据表 | 德州仪器 TI.com.cn

ZHCSIC7H March 2016 – November 2019 DRA722 , DRA724 , DRA725 , DRA726

PRODUCTION DATA.

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

ABC|760

散热焊盘机械数据 (封装 | 引脚)

订购信息

zhcsic7h_oa

7.16 Multichannel Serial Peripheral Interface (McSPI)

The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1, SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip selects) and are able to work as both master and slave.

The McSPI modules include the following main features:

Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of SPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode
Master multichannel mode:
- Full duplex/half duplex
- Transmit-only/receive-only/transmit-and-receive modes
- Flexible input/output (I/O) port controls per channel
- Programmable clock granularity
- SPI configuration per channel. This means, clock definition, polarity enabling and word width
Power management through wake-up capabilities
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel.
Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.

NOTE

For more information, see Multichannel Serial Peripheral Interface section in the device TRM.

NOTE

The McSPIm module (m = 1 to 4) is also referred to as SPIm.

CAUTION

The I/O timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETS are defined in Table 7-44.

Table 7-42, Figure 7-33 and Figure 7-34 present Timing Requirements for McSPI - Master Mode.

Table 7-42 Timing Requirements for SPI - Master Mode ^⁽¹⁾

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
SM1	t_c(SPICLK)	Cycle time, spi_sclk ^{⁽¹⁾⁽²⁾}	SPI1/2/3/4	20.8 ^⁽³⁾		ns
SM2	t_w(SPICLKL)	Typical Pulse duration, spi_sclk low ^⁽¹⁾		0.5 × P - 1 ^⁽⁴⁾		ns
SM3	t_w(SPICLKH)	Typical Pulse duration, spi_sclk high ^⁽¹⁾		0.5 × P - 1 ^⁽⁴⁾		ns
SM4	t_{su(MISO-SPICLK)}	Setup time, spi_d[x] valid before spi_sclk active edge ^⁽¹⁾		3.5		ns
SM5	t_{h(SPICLK-MISO)}	Hold time, spi_d[x] valid after spi_sclk active edge ^⁽¹⁾		3.7		ns
SM6	t_{d(SPICLK-SIMO)}	Delay time, spi_sclk active edge to spi_d[x] transition ^⁽¹⁾	SPI1	-3.57	4.1	ns
			SPI2	-3.9	3.6	ns
			SPI3	-4.9	4.7	ns
			SPI4	-4.3	4.5	ns
SM7	t_d(CS-SIMO)	Delay time, spi_cs[x] active edge to spi_d[x] transition			5	ns
SM8	t_d(CS-SPICLK)	Delay time, spi_cs[x] active to spi_sclk first edge ^⁽¹⁾	MASTER_PHA0 ^⁽⁵⁾	B - 4.2 ^⁽⁶⁾		ns
SM8	t_d(CS-SPICLK)	Delay time, spi_cs[x] active to spi_sclk first edge ^⁽¹⁾	MASTER_PHA1 ^⁽⁵⁾	A - 4.2 ^⁽⁷⁾		ns
SM9	t_d(SPICLK-CS)	Delay time, spi_sclk last edge to spi_cs[x] inactive ^⁽¹⁾	MASTER_PHA0 ^⁽⁵⁾	A - 4.2 ^⁽⁷⁾		ns
SM9	t_d(SPICLK-CS)	Delay time, spi_sclk last edge to spi_cs[x] inactive ^⁽¹⁾	MASTER_PHA1 ^⁽⁵⁾	B - 4.2 ^⁽⁶⁾		ns

This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data.
Related to the SPI_CLK maximum frequency.
20.8ns cycle time = 48MHz
P = SPICLK period.
SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
B = (TCS + 0.5) × TSPICLKREF × Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS + 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.

DRA722 DRA724 DRA725 DRA726 SPRS906_TIMING_McSPI_01.gif

Figure 7-33 McSPI - Master Mode Transmit

DRA722 DRA724 DRA725 DRA726 SPRS906_TIMING_McSPI_02.gif

Figure 7-34 McSPI - Master Mode Receive

Table 7-43, Figure 7-35 and Figure 7-36 present Timing Requirements for McSPI - Slave Mode.

Table 7-43 Timing Requirements for SPI - Slave Mode

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
SS1 ^⁽¹⁾	t_c(SPICLK)	Cycle time, spi_sclk		62.5 ^⁽²⁾^⁽³⁾		ns
SS2 ^⁽¹⁾	t_w(SPICLKL)	Typical Pulse duration, spi_sclk low		0.45 × P ^⁽⁴⁾		ns
SS3 ^⁽¹⁾	t_w(SPICLKH)	Typical Pulse duration, spi_sclk high		0.45 × P ^⁽⁴⁾		ns
SS4 ^⁽¹⁾	t_{su(SIMO-SPICLK)}	Setup time, spi_d[x] valid before spi_sclk active edge		5		ns
SS5 ^⁽¹⁾	t_{h(SPICLK-SIMO)}	Hold time, spi_d[x] valid after spi_sclk active edge		5		ns
SS6 ^⁽¹⁾	t_{d(SPICLK-SOMI)}	Delay time, spi_sclk active edge to mcspi_somi transition	SPI1/2/3	2	26.6	ns
SS6 ^⁽¹⁾	t_{d(SPICLK-SOMI)}	Delay time, spi_sclk active edge to mcspi_somi transition	SPI4	2	20.1	ns
SS7 ^⁽⁵⁾	t_d(CS-SOMI)	Delay time, spi_cs[x] active edge to mcspi_somi transition			20.95	ns
SS8 ^⁽¹⁾	t_{su(CS-SPICLK)}	Setup time, spi_cs[x] valid before spi_sclk first edge		5		ns
SS9 ^⁽¹⁾	t_h(SPICLK-CS)	Hold time, spi_cs[x] valid after spi_sclk last edge	SPI1/2	5		ns
			SPI3	7.5		ns
			SPI4	6		ns

This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data.
When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
62.5ns Cycle time = 16 MHz
P = SPICLK period.
PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.

DRA722 DRA724 DRA725 DRA726 SPRS906_TIMING_McSPI_03.gif

Figure 7-35 McSPI - Slave Mode Transmit

DRA722 DRA724 DRA725 DRA726 SPRS906_TIMING_McSPI_04.gif

Figure 7-36 McSPI - Slave Mode Receive

In Table 7-44 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4.

Table 7-44 McSPI3/4 IOSETs

SIGNALS	IOSET1		IOSET2		IOSET3		IOSET4		IOSET5
SIGNALS	BALL	MUX	BALL	MUX	BALL	MUX	BALL	MUX	BALL	MUX
McSPI3
spi3_cs0	D11	8	V9	7	A12	3	D17	2	AC9	1
spi3_cs1	B11	8	AC3	1	E14	3	B11	8	AC3	1
spi3_cs2	F11	8			F11	8	F11	8
spi3_cs3	A10	8			A10	8	A10	8
spi3_d0	C11	8	W9	7	B13	3	G16	2	AC6	1
spi3_d1	B10	8	Y1	7	A11	3	A21	2	AC7	1
spi3_sclk	E11	8	V2	7	B12	3	C18	2	AC4	1
McSPI4
spi4_cs0	P9	8	F3	8	U6	7	AA4	2	AB5	1
spi4_cs1	P4	8	P4	8	Y1	8	Y1	8	Y1	8
spi4_cs2	R3	8	R3	8	W9	8	W9	8	W9	8
spi4_cs3	T2	8	T2	8	V9	8	V9	8	V9	8
spi4_d0	N9	8	F2	8	V6	7	AB3	2	AB8	1
spi4_d1	R4	8	G6	8	U7	7	AB9	2	AD6	1
spi4_sclk	N7	8	G1	8	V7	7	AA3	2	AC8	1