ZHCSLL6C April   2021  – November 2024 DP83TC812R-Q1 , DP83TC812S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Electrostatic Discharge Sensing
        3. 7.3.1.3 Time Domain Reflectometry
        4. 7.3.1.4 Voltage Sensing
        5. 7.3.1.5 BIST and Loopback Modes
          1. 7.3.1.5.1 Data Generator and Checker
          2. 7.3.1.5.2 xMII Loopback
          3. 7.3.1.5.3 PCS Loopback
          4. 7.3.1.5.4 Digital Loopback
          5. 7.3.1.5.5 Analog Loopback
          6. 7.3.1.5.6 Reverse Loopback
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Down
      2. 7.4.2  Reset
      3. 7.4.3  Standby
      4. 7.4.4  Normal
      5. 7.4.5  Sleep Ack
      6. 7.4.6  Sleep Request
      7. 7.4.7  Sleep Fail
      8. 7.4.8  Sleep
      9. 7.4.9  Wake-Up
      10. 7.4.10 TC10 System Example
      11. 7.4.11 Media Dependent Interface
        1. 7.4.11.1 100BASE-T1 Master and 100BASE-T1 Slave Configuration
        2. 7.4.11.2 Auto-Polarity Detection and Correction
        3. 7.4.11.3 Jabber Detection
        4. 7.4.11.4 Interleave Detection
      12. 7.4.12 MAC Interfaces
        1. 7.4.12.1 Media Independent Interface
        2. 7.4.12.2 Reduced Media Independent Interface
        3. 7.4.12.3 Reduced Gigabit Media Independent Interface
        4. 7.4.12.4 Serial Gigabit Media Independent Interface
      13. 7.4.13 Serial Management Interface
        1. 7.4.13.1 Direct Register Access
        2. 7.4.13.2 Extended Register Space Access
        3. 7.4.13.3 Write Operation (No Post Increment)
        4. 7.4.13.4 Read Operation (No Post Increment)
        5. 7.4.13.5 Write Operation (Post Increment)
        6. 7.4.13.6 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Register Access Summary
      2. 7.6.2 DP83TC812 Registers
  9. 8 Application and Implementation
    1. 8.1 应用信息免责声明
    2. 8.2 Application Information
    3. 8.3 Typical Applications
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Physical Medium Attachment
          1. 8.3.1.1.1 Common-Mode Choke Recommendations
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Signal Traces
        2. 8.5.1.2 Return Path
        3. 8.5.1.3 Metal Pour
        4. 8.5.1.4 PCB Layer Stacking
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 支持资源
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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订购信息

7.6.2 DP83TC812 Registers

Table 7-28 lists the memory-mapped registers for the DP83TC812 registers. All register offset addresses not listed in Table 7-28 should be considered as reserved locations and the register contents should not be modified.

Table 7-28 DP83TC812 Registers
OffsetAcronymRegister NameSection
0hBMCRSection 7.6.2.1
1hBMSRSection 7.6.2.2
2hPHYIDR1Section 7.6.2.3
3hPHYIDR2Section 7.6.2.4
10hPHYSTSSection 7.6.2.5
11hPHYSCRSection 7.6.2.6
12hMISR1Section 7.6.2.7
13hMISR2Section 7.6.2.8
15hRECRSection 7.6.2.9
16hBISCRSection 7.6.2.10
18hMISR3Section 7.6.2.11
19hREG_19Section 7.6.2.12
1BhTC10_ABORT_REGSection 7.6.2.13
1EhCDCRSection 7.6.2.14
1FhPHYRCRSection 7.6.2.15
41hRegister_41Section 7.6.2.16
133hRegister_133Section 7.6.2.17
17FhRegister_17FSection 7.6.2.18
180hRegister_180Section 7.6.2.19
181hRegister_181Section 7.6.2.20
182hRegister_182Section 7.6.2.21
183hLPS_CFG4Section 7.6.2.22
184hLPS_CFGSection 7.6.2.23
185hLPS_CFG5Section 7.6.2.24
187hLPS_CFG7Section 7.6.2.25
188hLPS_CFG8Section 7.6.2.26
189hLPS_CFG9Section 7.6.2.27
18AhLPS_CFG10Section 7.6.2.28
18BhLPS_CFG2Section 7.6.2.29
18ChLPS_CFG3Section 7.6.2.30
18EhLPS_STATUSSection 7.6.2.31
300hTDR_TX_CFGSection 7.6.2.32
301hTAP_PROCESS_CFGSection 7.6.2.33
302hTDR_CFG1Section 7.6.2.34
303hTDR_CFG2Section 7.6.2.35
304hTDR_CFG3Section 7.6.2.36
305hTDR_CFG4Section 7.6.2.37
306hTDR_CFG5Section 7.6.2.38
310hTDR_TC1Section 7.6.2.39
430hA2D_REG_48Section 7.6.2.40
444hA2D_REG_68Section 7.6.2.41
450hLEDS_CFG_1Section 7.6.2.42
451hLEDS_CFG_2Section 7.6.2.43
452hIO_MUX_CFG_1Section 7.6.2.44
453hIO_MUX_CFG_2Section 7.6.2.45
456hIO_MUX_CFGSection 7.6.2.46
457hIO_STATUS_1Section 7.6.2.47
458hIO_STATUS_2Section 7.6.2.48
45DhCHIP_SOR_1Section 7.6.2.49
45FhLED1_CLKOUT_ANA_CTRLSection 7.6.2.50
485hPCS_CTRL_1Section 7.6.2.51
486hPCS_CTRL_2Section 7.6.2.52
489hTX_INTER_CFGSection 7.6.2.53
496hJABBER_CFGSection 7.6.2.54
497hTEST_MODE_CTRLSection 7.6.2.55
4A0hRXF_CFGSection 7.6.2.56
553hPG_REG_4Section 7.6.2.57
560hTC1_CFG_RWSection 7.6.2.58
561hTC1_LINK_FAIL_LOSSSection 7.6.2.59
562hTC1_LINK_TRAINING_TIMESection 7.6.2.60
600hRGMII_CTRLSection 7.6.2.61
601hRGMII_FIFO_STATUSSection 7.6.2.62
602hRGMII_CLK_SHIFT_CTRLSection 7.6.2.63
608hSGMII_CTRL_1Section 7.6.2.64
60AhSGMII_STATUSSection 7.6.2.65
60ChSGMII_CTRL_2Section 7.6.2.66
60DhSGMII_FIFO_STATUSSection 7.6.2.67
618hPRBS_STATUS_1Section 7.6.2.68
619hPRBS_CTRL_1Section 7.6.2.69
61AhPRBS_CTRL_2Section 7.6.2.70
61BhPRBS_CTRL_3Section 7.6.2.71
61ChPRBS_STATUS_2Section 7.6.2.72
61DhPRBS_STATUS_3Section 7.6.2.73
61EhPRBS_STATUS_4Section 7.6.2.74
620hPRBS_STATUS_5Section 7.6.2.75
622hPRBS_STATUS_6Section 7.6.2.76
623hPRBS_STATUS_7Section 7.6.2.77
624hPRBS_CTRL_4Section 7.6.2.78
625hPATTERN_CTRL_1Section 7.6.2.79
626hPATTERN_CTRL_2Section 7.6.2.80
627hPATTERN_CTRL_3Section 7.6.2.81
628hPMATCH_CTRL_1Section 7.6.2.82
629hPMATCH_CTRL_2Section 7.6.2.83
62AhPMATCH_CTRL_3Section 7.6.2.84
639hTX_PKT_CNT_1Section 7.6.2.85
63AhTX_PKT_CNT_2Section 7.6.2.86
63BhTX_PKT_CNT_3Section 7.6.2.87
63ChRX_PKT_CNT_1Section 7.6.2.88
63DhRX_PKT_CNT_2Section 7.6.2.89
63EhRX_PKT_CNT_3Section 7.6.2.90
648hRMII_CTRL_1Section 7.6.2.91
649hRMII_STATUS_1Section 7.6.2.92
64AhRMII_OVERRIDE_CTRLSection 7.6.2.93
871hdsp_reg_71Section 7.6.2.94
1000hMMD1_PMA_CTRL_1Section 7.6.2.95
1001hMMD1_PMA_STATUS_1Section 7.6.2.96
1007hMMD1_PMA_STAUS_2Section 7.6.2.97
100BhMMD1_PMA_EXT_ABILITY_1Section 7.6.2.98
1012hMMD1_PMA_EXT_ABILITY_2Section 7.6.2.99
1834hMMD1_PMA_CTRL_2Section 7.6.2.100
1836hMMD1_PMA_TEST_MODE_CTRLSection 7.6.2.101
3000hMMD3_PCS_CTRL_1Section 7.6.2.102
3001hMMD3_PCS_Status_1Section 7.6.2.103

Complex bit access types are encoded to fit into small table cells. Table 7-29 shows the codes that are used for access types in this section.

Table 7-29 DP83TC812 Access Type Codes
Access TypeCodeDescription
Read Type
HHSet or cleared by hardware
RRRead
RCR
C		Read
to Clear
RHR
H		Read
Set or cleared by hardware
Write Type
WWWrite
W0SW
0S		Write
0 to set
W1SW
1S		Write
1 to set
WSCWWrite
Reset or Default Value
-nValue after reset or the default value

7.6.2.1 BMCR Register (Offset = 0h) [Reset = 2100h]

BMCR is shown in Table 7-30.

Return to the Summary Table.

Table 7-30 BMCR Register Field Descriptions
BitFieldTypeResetDescription
15MII_reset RH/W1S0h MII Reset. This bit will reset the Digital blocks of the PHY and return registers 0x0-0x0F back to default values. Other register will not be affected.
0h = No reset
1h = Digital in reset and all MII regs (0x0 - 0xF) reset to default
14xMII Loopback R/W0h xMII Loopback: 1 = xMII Loopback enabled 0 = Normal Operation When xMII loopback mode is activated, the transmitted data presented on xMII TXD is looped back to xMII RXD internally. There is no LINK indication generated when xMII loopback is enabled.
1h = Enable Loopback from G/MII input to G/MII output
13Manual_speed_MIIR1h Speed Selection: Always 100-Mbps Speed
12Auto-Negotiation EnableR0h Auto-Negotiation: Not supported on this device
0h = Disable Auto-Negotiation
11Power DownR/W0h Power Down: The PHY is powered down after this bit is set. Only register access is enabled during this power down condition.
The power down mode can be controlled via this bit or via INT_N pin. INT_N pin needs to be configured to operate as power down control. This bit is OR-ed with the input from the INT_N pin. When the active low INT_N is asserted, this bit is set.
0h = Normal Mode
1h = IEEE Power Down
10IsolateR/W0h Isolate:Isolates the port from the xMII with the exception of the serial management interface
0h = Normal Mode
1h = Enable Isolate Mode
9RESERVEDR0h Reserved
8Duplex ModeR1h 1 = Full Duplex 0 = Half duplex
0h = Half duplex
1h = Full Duplex
7RESERVEDR/W0h Reserved
6-0RESERVEDR0h Reserved

7.6.2.2 BMSR Register (Offset = 1h) [Reset = 0061h]

BMSR is shown in Table 7-31.

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Table 7-31 BMSR Register Field Descriptions
BitFieldTypeResetDescription
15100Base-T4R0h Always 0 - PHY not able to perform 100Base-T4
14100Base-X Full DuplexR0h 1 = PHY able to perform full duplex 100Base-X 0 = PHY not able to perform full duplex 100Base-X
0h = PHY not able to perform full duplex 100Base-X
1h = PHY able to perform full duplex 100Base-X
13100Base-X Half DuplexR0h 1 = PHY able to perform half duplex 100Base-X 0 = PHY not able to perform half duplex 100Base-X
0h = PHY not able to perform half duplex 100Base-X
1h = PHY able to perform half duplex 100Base-X
1210 Mbps Full DuplexR0h 1 = PHY able to operate at 10Mbps in full duplex 0 = PHY not able to operate at 10Mbps in full duplex
0h = PHY not able to operate at 10Mbps in full duplex
1h = PHY able to operate at 10Mbps in full duplex
1110 Mbps Half DuplexR0h 1 = PHY able to operate at 10Mbps in half duplex 0 = PHY not able to operate at 10Mbps in half duplex
0h = PHY not able to operate at 10Mbps in half duplex
1h = PHY able to operate at 10Mbps in half duplex
10-7RESERVEDR0h Reserved
6MF Preamble SuppressionR1h 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed
0h = PHY will not accept management frames with preamble suppressed
1h = PHY will accept management frames with preamble suppressed
5Auto-Negotiation CompleteR1h 1 = Auto-Negotiation process completed 0 = Auto Negotiation process not completed (either still in process, disabled or reset)
0h = Auto Negotiation process not completed (either still in process, disabled or reset)
1h = Auto-Negotiation process completed
4Remote faultH0h 1 = Remote fault condition detected 0 = No remote fault condition detected
0h = No remote fault condition detected
1h = Remote fault condition detected
3Auto-Negotiation AbilityR0h 1 = PHY is able to perform Auto-Negotiation 0 = PHY is not able to perform Auto-Negotiation
0h = PHY is not able to perform Auto-Negotiation
1h = PHY is able to perform Auto-Negotiation
1jabber detectH0h 1= jabber condition detected 0 = No jabber condition detected
0h = No jabber condition detected
1h = jabber condition detected
0Extended CapabilityR1h 1 = Extended register capabilities 0 = Basic register set capabilities only
0h = Basic register set capabilities only
1h = Extended register capabilities

7.6.2.3 PHYIDR1 Register (Offset = 2h) [Reset = 2000h]

PHYIDR1 is shown in Table 7-32.

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Table 7-32 PHYIDR1 Register Field Descriptions
BitFieldTypeResetDescription
15-0Organizationally Unique Identifier Bits 21:6R2000h Organizationally Unique Identification Number

7.6.2.4 PHYIDR2 Register (Offset = 3h) [Reset = A271h]

PHYIDR2 is shown in Table 7-33.

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Table 7-33 PHYIDR2 Register Field Descriptions
BitFieldTypeResetDescription
15-10Organizationally Unique Identifier Bits 5:0R28h Organizationally Unique Identification Number
9-4Model NumberR27h Vendor Model Number: The six bits of vendor model number are mapped from bits 9 to 4
3-0Revision NumberR1h Device Revision Number
0h = Silicon Rev 1.0
1h = Silicon Rev 2.0

7.6.2.5 PHYSTS Register (Offset = 10h) [Reset = 0004h]

PHYSTS is shown in Table 7-34.

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Table 7-34 PHYSTS Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14RESERVEDR0h Reserved
13receive_error_latchH0h RxerrCnt0 since last read.clear on read
12RESERVEDH0h Reserved
11RESERVEDH0h Reserved
10signal_detectR/W0S0h Channel ok latch low
0h = Channel ok had been reset
1h = Channel ok is set
9descrambler_lockR/W0S0h Descrambler lock latch low
0h = Descrmabler had been locked
1h = Descrambler is locked
8RESERVEDR0h Reserved
7mii_interruptH0h Interrupts pin status, cleared on reading 0x12 1b0 = Interrupts pin not set 1b1 = Interrupt pin had been set
6RESERVEDR0h Reserved
5jabber_dtctR0h duplicate from reg.0x1.1
4RESERVEDH0h Reserved
3loopback_statusR0h MII loopback status
0h = No MII loopback
1h = MII loopback
2duplex_statusR1h Duplex mode status
0h = Half duplex
1h = Full duplex
1RESERVEDR0h Reserved

7.6.2.6 PHYSCR Register (Offset = 11h) [Reset = 010Bh]

PHYSCR is shown in Table 7-35.

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Table 7-35 PHYSCR Register Field Descriptions
BitFieldTypeResetDescription
15dis_clk_125R/W0h 1 = Disable CLK125 (Sourced by the CLK125 port)
1h = Disable CLK125 (Sourced by the CLK125 port)
14pwr_save_mode_enR/W0h Enable power save mode config from reg
13-12pwr_save_modeR/W0h Power Save Mode
0h = Normal mode
1h = IEEE mode: power down all digital and analog blocks, if bit [11] set to zero, PLL is also powered down 10 = Reserved 11 = Reserved
11sgmii_soft_resetR/WSC0h Reset SGMII
10use_PHYAD0_as_IsolateR/W0h 1- when phy_addr == 0, isolate MAC Interface 0- do not Isolate for PHYAD == 0.
0h = do not Isolate for PHYAD is 0.
1h = when phy_addr is 0, isolate MAC Interface
9-8tx_fifo_depthR/W1h RMII TX fifo depth
0h = 4 nibbles
1h = 5 nibbles
Ah = 6 nibbles
Bh = 8 nibbles
7RESERVEDR/W0h Reserved
6-4RESERVEDR0h Reserved
3int_polR/W1h Interrupt Polarity
0h = Steady state (normal operation) without an interrupt is logical 0; during interrupt, pin is logical 1
1h = Steady state (normal operation) without an interrupt is logical 1; during interrupt, pin is logical 0
2force_interruptR/W0h Force interrupt pin
0h = Do not force interrupt pin
1h = Force interrupt pin
1INTENR/W1h Enable interrupts
0h = Disable interrupts
1h = Enable interrupts
0INT_OER/W1h Interrupt/Power down pin configuration
0h = PIN is a power down PIN (input)
1h = PIN is an interrupt pin (output)

7.6.2.7 MISR1 Register (Offset = 12h) [Reset = 0000h]

MISR1 is shown in Table 7-36.

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Table 7-36 MISR1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDH0h Reserved
14energy_det_intH0h This INT can be asserted upon Rising edge only of energy_det signal using reg0x101 bit [0] : cfg_energy_det_int_le_only. status output of energy_det_hist signal on reg0x19 bit[10].
0h = No Change of energy detected
1h = Change of energy_detected (both rising and falling edges)
12wol_intH0h Interrupt bit indicating that WOL packet is received
0h = No WoL interrupt pending.
1h = WoL packet received interrupt is pending and is cleared by the current read.
11esd_intH0h 1 = ESD detected interrupt is pending and is cleared by the current read. 0 = No ESD interrupt pending.
10ms_train_done_intH0h 1 = M/S Link Training Completed interrupt is pending and is cleared by the current read. 0 = No M/S Link Training Completed interrupt pending.
9fhf_intH0h 1 = False carrier counter half-full interrupt is pending and is cleared by the current read. 0 = No false carrier counter half-full interrupt pending.
8rhf_intH0h 1 = Receive error counter half-full interrupt is pending and is cleared by the current read. 0 = No receive error carrier counter half-full interrupt pending.
7RESERVEDR/W0h Reserved
6energy_det_int_enR/W0h Enable Interrupt on change of Energy Detect histr. Status
4wol_int_enR/W0h Enable Interrupt on WoL detection
3esd_int_enR/W0h Enable Interrupt on ESD detect event
2ms_train_done_int_enR/W0h Enable Interrupt on M/S Link Training Completed event
1fhf_int_enR/W0h Enable Interrupt on False Carrier Counter Register half-full event
0rhf_int_enR/W0h Enable Interrupt on Receive Error Counter Register half-full event

7.6.2.8 MISR2 Register (Offset = 13h) [Reset = 0000h]

MISR2 is shown in Table 7-37.

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Table 7-37 MISR2 Register Field Descriptions
BitFieldTypeResetDescription
15under_volt_intH0h 1 = Under Voltage has been detected 0 =Under Voltage has not been detected
0h = Under Voltage has not been detected
1h = Under Voltage has been detected
14over_volt_intH0h 1 = Over Voltage has been detected 0 = Over Voltage has not been detected
0h = Over Voltage has not been detected
1h = Over Voltage has been detected
13RESERVEDH0h Reserved
12RESERVEDH0h Reserved
11RESERVEDH0h Reserved
10sleep_intH0h 1 = Sleep mode has changed 0 = Sleep mode has not changed
0h = Sleep mode has not changed
1h = Sleep mode has changed
9pol_intH0h The device has auto-polarity correction when operating in slave mode. This bit will reflect if polarity was automatically swapped or not.
0h = Data polarity has not changed
1h = Data polarity has changed
8jabber_intH0h 1 = Jabber detected 0 = Jabber not detected
0h = Jabber not detected
1h = Jabber detected
7under_volt_int_enR/W0h 0 = Disable interrupt
0h = Disable interrupt
6over_volt_int_enR/W0h 0 = Disable interrupt
0h = Disable interrupt
5page_rcvd_int_enR/W0h 1 = Enable interrupt
1h = Enable interrupt
4Fifo_int_enR/W0h 1 = Enable interrupt
1h = Enable interrupt
3RESERVEDR/W0h Reserved
2sleep_int_enR/W0h 1 = Enable interrupt
1h = Enable interrupt
1pol_int_enR/W0h 1 = Enable interrupt
1h = Enable interrupt
0jabber_int_enR/W0h 1 = Enable interrupt
1h = Enable interrupt

7.6.2.9 RECR Register (Offset = 15h) [Reset = 0000h]

RECR is shown in Table 7-38.

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Table 7-38 RECR Register Field Descriptions
BitFieldTypeResetDescription
15-0`RC0h RX_ER Counter: When a valid carrier is presented (only while RX_DV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in xMII loopback mode. The counter stops when it reaches its maximum count (0xFFFF). When the counter exceeds half-full (0x7FFF), an interrupt is generated. This register is cleared on read.

7.6.2.10 BISCR Register (Offset = 16h) [Reset = 0100h]

BISCR is shown in Table 7-39.

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Table 7-39 BISCR Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10prbs_sync_lossH0h Prbs lock lost latch status
0h = Prbs lock never lost
1h = Prbs lock had been lost
9RESERVEDR0h Reserved
8core_pwr_modeR1h 1b0 = Core is in power down or sleep mode 1b1 = Core is is normal power mode
0h = Core is in power down or sleep mode
1h = Core is is normal power mode
7RESERVEDR0h Reserved
6tx_mii_lpbkR/W0h Transmit data control during xMII Loopback
0h = Suppress data during xMII loopback
1h = Transmit data on MDI during xMII loopback
5-2loopback_modeR/W0h Loopback Modes (Bit [1:0] should be 0)
1h = Digital Loopback
2h = Analog Loopback
4h = Reverse Loopback
8h = External Loopback
1pcs_lpbckR/W0h PCS loopback after PAM3
0h = Disable PCS Loopback
1h = Enable PCS Loopback
0RESERVEDR/W0h Reserved

7.6.2.11 MISR3 Register (Offset = 18h) [Reset = 00X5h]

MISR3 is shown in Table 7-40.

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Table 7-40 MISR3 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDH0h Reserved
13sleep_fail_intH0h
0h = Sleep negotiation not failed yet
1h = Sleep negotiation failed
12POR_done_intH0h
0h = POR not completed yet
1h = POR completed (required for re-initialization of registers when we come out of sleep)
11no_frame_intH0h
0h = Frame was detected
1h = No Frame detected for transmission or reception in given time
10wake_req_intH0h
0h = Wake-up request not received
1h = Wake-up request command was received from remote PHY
9WUP_sleep_intH0h
0h = WUP not received
1h = WUP received from remote PHY when in sleep
8LPS_intH0h
0h = LPS symbols not detected
1h = LPS symbols detetced
7wup_psv_int_enR/WXh
0h = Disable interrupt
1h = Enable interrupt
5sleep_fail_int_enR/W1h
0h = Disable interrupt
1h = Enable interrupt
4POR_done_int_enR/W0h
0h = Disable interrupt
1h = Enable interrupt
3no_frame_int_enR/W0h
0h = Disable interrupt
1h = Enable interrupt
2wake_req_int_enR/W1h
0h = Disable interrupt
1h = Enable interrupt
1WUP_sleep_int_enR/W0h
0h = Disable interrupt
1h = Enable interrupt
0LPS_int_enR/W1h
0h = Disable interrupt
1h = Enable interrupt

7.6.2.12 REG_19 Register (Offset = 19h) [Reset = 0800h]

REG_19 is shown in Table 7-41.

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Table 7-41 REG_19 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0h Reserved
13RESERVEDR0h Reserved
12RESERVEDR0h Reserved
11RESERVEDR0h Reserved
10dsp_energy_detectR0h DSP energy detected status
9-5RESERVEDR0h Reserved
4-0PHY_ADDRR0h PHY address decode from straps

7.6.2.13 TC10_ABORT_REG Register (Offset = 1Bh) [Reset = 0000h]

TC10_ABORT_REG is shown in Table 7-42.

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Table 7-42 TC10_ABORT_REG Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1cfg_tc10_abort_gpio_enR/W0h enables aborting TC10 via GPIO. one of CLKOUT/LED_1 pins which is being used as an LED can be used to abort
0h = disable TC10 abort via GPIO
1h = enable TC10 abort via GPIO
0cfg_sleep_abortR/W0h loc_sleep_abprt as defined by TC10 standard. Aborts sleep negotiation while in SLEEP_ACK state
0h = allow TC10 sleep negotiation
1h = abort TC10 sleep negotiation

7.6.2.14 CDCR Register (Offset = 1Eh) [Reset = 0000h]

CDCR is shown in Table 7-43.

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Table 7-43 CDCR Register Field Descriptions
BitFieldTypeResetDescription
15tdr_start RH/W1S0h clr by tdr done Start TDR manually
0h = No TDR
1h = TDR start
14cfg_tdr_auto_runR/W0h Enable TDR auto run on link down
0h = TDR start manually
1h = TDR start automatically on link down
13-2RESERVEDR0h Reserved
1tdr_done R0h TDR done status
0h = TDR still not done
1h = TDR done
0tdr_failR0h TDR fail status

7.6.2.15 PHYRCR Register (Offset = 1Fh) [Reset = 0000h]

PHYRCR is shown in Table 7-44.

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Table 7-44 PHYRCR Register Field Descriptions
BitFieldTypeResetDescription
15Software Global ResetRH/W1S0h Hardware Reset(Reset digital + register file)
0h = Normal Operation
1h = Resets PHY and clears registers. Does not resample the straps. This bit is self cleared.
14Digital resetRH/W1S0h Software Restart
0h = Normal Operation
1h = Restart PHY. Resets PHY but does not clear registers. Does not resample the straps. This bit is self cleared.
13RESERVEDR/W0h Reserved
12-8RESERVEDR/W0h Reserved
7Standby_modeR/W0h Standby Mode
0h = Normal operation
1h = Standby mode enabled
6RESERVEDR/W0h Reserved
5RESERVEDR0h Reserved
4-0RESERVEDR/W0h Reserved

7.6.2.16 Register_41 (Offset = 41h) [Reset = 88F7h]

Register_41 is shown in Table 7-45.

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Table 7-45 Register_41 Field Descriptions
BitFieldTypeResetDescription
15-0cfg_ether_type_patternR/W88F7h Ethertype pattern to be detected when 0x40[0] is enabled

7.6.2.17 Register_133 (Offset = 133h) [Reset = 0000h]

Register_133 is shown in Table 7-46.

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Table 7-46 Register_133 Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
11-8RESERVEDR0h Reserved
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5RESERVEDR0h Reserved
4RESERVEDR0h Reserved
3RESERVEDR0h Reserved
2descr_syncR0h Status of descrambler
0h = Scrambler Not Locked
1h = Scrambler Locked
1loc_rcvr_statusR0h Local receiver status
0h = Local PHY received link invalid
1h = Local PHY received link valid
0rem_rcvr_statusR0h Remote receiver status
0h = Remote PHY received link invalid
1h = Remote PHY received link valid

7.6.2.18 Register_17F (Offset = 17Fh) [Reset = 4028h]

Register_17F is shown in Table 7-47.

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Table 7-47 Register_17F Field Descriptions
BitFieldTypeResetDescription
15cfg_en_wur_via_wakeR/W0h enable sending WUR when wake pin is asserted during active link. Duration of pulse on WAKE pin can be configured in 0x17F[7:0]
0h = disable sending WUR when pulse on wake pin
1h = enable sending WUR when pulse on wake pin
14cfg_en_wup_via_wakeR/W1h enable sending WUP when device is woken by WAKE pin
0h = disables WUP
1h = enables WUP
13-8RESERVEDR0h Reserved
7-0cfg_wake_pin_len_fr_wur_thR/W28h Width of pulse in microseconds required to initiate WUR during an active link

7.6.2.19 Register_180 (Offset = 180h) [Reset = 0000h]

Register_180 is shown in Table 7-48.

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Table 7-48 Register_180 Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0h Reserved
4-3cfg_sleep_req_timer_selR/W0h Configure sleep request timer
0h = 16ms
1h = 4ms
2h = 32ms
3h = 40ms
2RESERVEDR0h Reserved
1-0cfg_sleep_ack_timer_selR/W0h Configure sleep acknowledge timer
0h = 8ms
1h = 6ms
2h = 24ms
3h = 32ms

7.6.2.20 Register_181 (Offset = 181h) [Reset = 0000h]

Register_181 is shown in Table 7-49.

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Table 7-49 Register_181 Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0h Reserved
9-0rx_lps_cntR0h indicates number of LPS codes received

7.6.2.21 Register_182 (Offset = 182h) [Reset = 0000h]

Register_182 is shown in Table 7-50.

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Table 7-50 Register_182 Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0h Reserved
9-0tx_lps_cntR0h indicates number of WUR codes received

7.6.2.22 LPS_CFG4 Register (Offset = 183h) [Reset = 0000h]

LPS_CFG4 is shown in Table 7-51.

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Table 7-51 LPS_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
15cfg_send_wup_dis_tx R/W0h Write 1 to this bit to send WUP when PHY control is in DISABLE_TRANSMIT state
14cfg_force_lps_sleep_enR/W0h force control enable for sleep from LPS SM to PHY control SM
13cfg_force_lps_sleepR/W0h force value for sleep from LPS SM to PHY control SM
12cfg_force_tx_lps_enR/W0h force enable for TX_LPS
11cfg_force_tx_lpsR/W0h force value for TX_LPS
8cfg_force_lps_st_enR/W0h force enable for LPS state machine
7RESERVEDR0h Reserved
6-0cfg_force_lps_stR/W0h force value of LPS state machine

7.6.2.23 LPS_CFG Register (Offset = 184h) [Reset = 0223h]

LPS_CFG is shown in Table 7-52.

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Table 7-52 LPS_CFG Register Field Descriptions
BitFieldTypeResetDescription
15cfg_reset_wur_cnt_rx_dataR/W0h When set, resets the WUR received symbol counter upon receiving data
14-13RESERVEDR0h Reserved
12cfg_reset_lps_cnt_rx_dataR/W0h When set, resets the LPS received symbol counter upon receiving data
11-10RESERVEDR0h Reserved
9cfg_reset_wur_cnt_tx_dataR/W1h When set, resets the transmitted WUR symbols count when sending data
8-7RESERVEDR0h Reserved
6cfg_reset_lps_cnt_tx_dataR/W0h When set, resets the transmitted LPS symbols count when sending data
4cfg_wake_fwd_man_trigR/W0h Write 1 to manually generate Wake forwarding signal on WAKE pin. This bit is self-cleared
3-2cfg_wake_fwd_dig_timerR/W0h when wake up request is received on an active link, the width of wake forwarding pulses are configurable to : 00: 50us 01: 500us 10: 2ms 11: 20ms
1cfg_wake_fwd_en_wurR/W1h If set, enables doing wake forwarding when WUR symbols are received
0h = Don 't do wake forwarding on WAKE pin
1h = do wake forwarding on WAKE pin
0cfg_wake_fwd_en_wupR/W1h If set, enables doing wake forwarding when WUP symbols are received
0h = Don 't do wake forwarding on WAKE pin
1h = do wake forwarding on WAKE pin

7.6.2.24 LPS_CFG5 Register (Offset = 185h) [Reset = 0000h]

LPS_CFG5 is shown in Table 7-53.

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Table 7-53 LPS_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
15-13cfg_wup_timerR/W0h Time for which PHY control SM stays in WAKE_TRANSMIT b000: 1ms b001: 0.7ms b010: 1.3ms b011: 0.85ms b100: 1.5ms b101: 2ms b110: 2.5ms b111: 3ms
12-4RESERVEDR0h Reserved
3-2cfg_rx_wur_sym_gapR/W0h max gap allowed b/w two WUR symbols for ack of WUR
1-0cfg_rx_lps_sym_gapR/W0h max gap allowed b/w two LPS symbols for ack of LPS

7.6.2.25 LPS_CFG7 Register (Offset = 187h) [Reset = 0000h]

LPS_CFG7 is shown in Table 7-54.

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Table 7-54 LPS_CFG7 Register Field Descriptions
BitFieldTypeResetDescription
15cfg_tx_lps_stop_on_doneR/W0h configures the device to stop sending LPS codes once it is done sending the number of codes configures in 0x1879:0
0h = continues even after reaching limit
1h = stops after reaching limit
14-8RESERVEDR0h Reserved
9-0cfg_tx_lps_selR/W0h Indicates number of LPS symbols to be transmitted before tx_lps_done becomes true

7.6.2.26 LPS_CFG8 Register (Offset = 188h) [Reset = 0080h]

LPS_CFG8 is shown in Table 7-55.

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Table 7-55 LPS_CFG8 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0h Reserved
9-0cfg_tx_wur_selR/W80h Indicates number of WUR symbols to be transmitted

7.6.2.27 LPS_CFG9 Register (Offset = 189h) [Reset = 0040h]

LPS_CFG9 is shown in Table 7-56.

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Table 7-56 LPS_CFG9 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0h Reserved
9-0cfg_rx_lps_selR/W40h Indicates number of LPS symbols to be received to set lps_recv

7.6.2.28 LPS_CFG10 Register (Offset = 18Ah) [Reset = 0040h]

LPS_CFG10 is shown in Table 7-57.

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Table 7-57 LPS_CFG10 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0h Reserved
9-0cfg_rx_wur_selR/W40h Indicates number of WUR symbols to be received to acknowlege WUR and do wake forwarding

7.6.2.29 LPS_CFG2 Register (Offset = 18Bh) [Reset = 1C4Bh]

LPS_CFG2 is shown in Table 7-58.

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Table 7-58 LPS_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12cfg_stop_sleep_neg_on_no_send_nR/W1h If this bit is set, TC10 statemachine reverts back to NORMAL state from SLEEP_ACK or SLEEP_REQ states when Link is dropped
11cfg_stop_sleep_neg_on_activityR/W1h When packets are either transmitted or received by the PHY, setting this bit Stops sleep negotiation and TC10 state machine reverts back to NORMAL state when it is in SLEEP_ACK or SLEEP_REQ state(when sleep negotiation is ongoing)
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7RESERVEDR0h Ignore on read
6cfg_auto_mode_enR/W1h LPS autonomous mode enable if(RX_D3_strap ==1) reset_val = ~CLKOUT_strap else reset_val = ~LED_1_strap This bit is Auto-cleared after Link-Up
0h = AUTO mode disabled
1h = AUTO mode enable
5cfg_lps_mon_enR/W0h Normal to Standby Transition Enable
0h = Disable normal to standby transition on over temp/under volt
1h = Enable normal to standby transition on over temp/under volt
4RESERVEDR/W0h Reserved
3RESERVEDR/W0h Reserved
2RESERVEDR/W0h Reserved
1cfg_lps_sleep_enR/W1h Enable transition to Standby mode instead of Sleep mode after successful sleep negotiation (refered to as TC10_SBY)
0h = Enter standby after negotiated LPS
1h = Enter sleep after negotiated LPS
0RESERVEDR/W0h Reserved

7.6.2.30 LPS_CFG3 Register (Offset = 18Ch) [Reset = 0000h]

LPS_CFG3 is shown in Table 7-59.

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Table 7-59 LPS_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h Reserved
8-0cfg_lps_pwr_modeRH/W1S0h
001h = Normal command
002h = Sleep request
010h = Standby command
080h = WUR command

7.6.2.31 LPS_STATUS Register (Offset = 18Eh) [Reset = 0000h]

LPS_STATUS is shown in Table 7-60.

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Table 7-60 LPS_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR0h Reserved
6-0status_lps_stR0h LPS SM state
01h = SLEEP
02h = STANDBY
04h = NORMAL
08h = SLEEP_ACK
10h = SLEEP_REQ
20h = SLEEP_FAIL
40h = SLEEP_SILENT
41h = PASSIVE_LINK

7.6.2.32 TDR_TX_CFG Register (Offset = 300h) [Reset = 2710h]

TDR_TX_CFG is shown in Table 7-61.

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Table 7-61 TDR_TX_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-0cfg_tdr_tx_durationR/W2710h TDR transmit duration in usec, Default : 10000usec

7.6.2.33 TAP_PROCESS_CFG Register (Offset = 301h) [Reset = 1703h]

TAP_PROCESS_CFG is shown in Table 7-62.

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Table 7-62 TAP_PROCESS_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12-8cfg_end_tap_indexR/W17h End echo coefficient index for peak detect sweep during TDR
7-5RESERVEDR0h Reserved
4-0cfg_start_tap_indexR/W3h Starting echo coefficient index for peak detect sweep during TDR

7.6.2.34 TDR_CFG1 Register (Offset = 302h) [Reset = 0045h]

TDR_CFG1 is shown in Table 7-63.

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Table 7-63 TDR_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0h Reserved
7-4cfg_forward_shadowR/W4h Num of neighboring echo coeff taps to be considered for calculating local maximum
3-2cfg_post_silence_timeR/W1h Post-Silence state timer in ms 0x00 : 0ms 0x01 : 10ms 0x10 : 100ms 0x11 : 1000ms
1-0cfg_pre_silence_timeR/W1h Pre-Silence state timer in ms 0x00 : 0ms 0x01 : 10ms 0x10 : 100ms 0x11 : 1000ms

7.6.2.35 TDR_CFG2 Register (Offset = 303h) [Reset = 0419h]

TDR_CFG2 is shown in Table 7-64.

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Table 7-64 TDR_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12-8cfg_tdr_filt_loc_offsetR/W4h tap index offset of dyamic peak equation, cfg_start_tap_index + 1'b1
7-0cfg_tdr_filt_initR/W19h Value of peak_th at x=start_tap_index of dynamic peak threshold equation

7.6.2.36 TDR_CFG3 Register (Offset = 304h) [Reset = 0030h]

TDR_CFG3 is shown in Table 7-65.

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Table 7-65 TDR_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0h Reserved
7-0cfg_tdr_filt_slopeR/W30h Slope of dynamic peak threshold equation (0.4)

7.6.2.37 TDR_CFG4 Register (Offset = 305h) [Reset = 0004h]

TDR_CFG4 is shown in Table 7-66.

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Table 7-66 TDR_CFG4 Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0h Reserved
9RESERVEDR/W0h Reserved
8-7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5-4hpf_gain_tdrR/W0h HPF gain code during TDR
3-0pga_gain_tdrR/W4h PGA gain code during TDR

7.6.2.38 TDR_CFG5 Register (Offset = 306h) [Reset = 000Ah]

TDR_CFG5 is shown in Table 7-67.

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Table 7-67 TDR_CFG5 Register Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0h Reserved
4cfg_half_open_det_enR/W0h enables detection of half cable
0h = Disables half open detection
1h = Enbales half open detection
3-0cfg_cable_delay_numR/WAh Configure the propagation delay per meter of the cable in nanoseconds. This is used for the fault location estimation Valid values : 4 'd0 to 4 'd11 - [4.5:0.1:5.6]ns Default : 4 'd10 (5.5 ns)

7.6.2.39 TDR_TC1 Register (Offset = 310h) [Reset = 0000h]

TDR_TC1 is shown in Table 7-68.

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Table 7-68 TDR_TC1 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h Reserved
8half_open_detectR0h Half wire open detect value
0h = Half wire open not detected
1h = Half wire open detected
7peak_detectR0h Set if fault is detected in cable
0h = Fault not detected in cable
1h = Fault detected in cable
6peak_signR0h Nature of discontinuity. Valid only if peak_detect is set
0h = Short to GND, supply, or between MDI pins
1h = Open. Applicable to both 1-wire and 2-wire open faults
5-0peak_loc_in_metersR0h Fault location in meters (Valid only if peak_detect is set)

7.6.2.40 A2D_REG_48 Register (Offset = 430h) [Reset = 0770h]

A2D_REG_48 is shown in Table 7-69.

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Table 7-69 A2D_REG_48 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12RESERVEDR/W0h Reserved
11-8dll_tx_delay_ctrl_rgmii_slR/W7h controls TX DLL in RGMII mode inSteps of 312.5ps, affects the CLK_90 output.
Delay = ((Bit[11:8] in decimal) + 1)*312.5 ps
7-4dll_rx_delay_ctrl_rgmii_slR/W7h Controls RX DLL in RGMII mode in Steps of 312.5ps, affects the CLK_90 output.
Delay = ((Bit[7:4] in decimal) + 1)*312.5 ps
3-0RESERVEDR/W0h Reserved

7.6.2.41 A2D_REG_68 Register (Offset = 444h) [Reset = 0000h]

A2D_REG_68 is shown in Table 7-70.

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Table 7-70 A2D_REG_68 Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0h Reserved
3goto_sleep_force_valR/W0h Sleep Mode Force Value:
2goto_sleep_force_controlR/W0h Sleep Mode Force Control:
1wake_fwd_force_valR/W0h WAKE Output Force Value:
0h = Force low on WAKE pin if 0x0444[0]=1
1h = Force high on WAKE pin if 0x444[0]=1
0wake_fwd_force_controlR/W0h WAKE Output Value Force Control:
0h = Force Control Disable.
1h = Force Control Enable. Output value is set by 0x0444[1]

7.6.2.42 LEDS_CFG_1 Register (Offset = 450h) [Reset = 2610h]

LEDS_CFG_1 is shown in Table 7-71.

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Table 7-71 LEDS_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14leds_bypass_stretchingR/W0h
0h = Normal Operation
1h = Bypass LEDs stretching
11-8led_2_optionR/W6h Controlls LED_2 sources
(same as bits 3:0)
7-4led_1_optionR/W1h Controlls LED_1 sources
(same as bits 3:0)
3-0led_0_optionR/W0h Controlls LED_0 source:
0h = link OK
1h = link OK + blink on TX/RX activity
2h = link OK + blink on TX activity
3h = link OK + blink on RX activity
4h = link OK + 100Base-T1 Master
5h = link OK + 100Base-T1 Slave
6h = TX/RX activity with stretch option
7h = Reserved
8h = Reserved
9h = Link lost (remains on until register 0x1 is read)
Ah = PRBS error (toggles on error)
Bh = XMII TX/RX Error with stretch option

7.6.2.43 LEDS_CFG_2 Register (Offset = 451h) [Reset = 0049h]

LEDS_CFG_2 is shown in Table 7-72.

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Table 7-72 LEDS_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
15clk_o_gpio_ctrl_3R/W0h MSB of CLKOUT gpio control. This bit provides additional options for configuring CLKOUT
If set to 1, it changes the effect ofclk_o_gpio_ctrl bits of 0x453
Reg 0x453[2:0] will control CLKOUT as follows

0h = pwr_seq_done
1h = loc_wake_req from analog
2h = loc_wake_req to PHY control
3h = tx_lps_done
4h = tx_lps_done_64
5h = tx_lps
6h = pcs rx sm - receiving
7h = pcs tx sm - tx_enable
14led_1_gpio_ctrl_3R/W0h MSB of LED_1 gpio control. This bit provides additional options for configuring LED_0
If set to 1, it changes the effect of led_1_gpio_ctrl bits of 0x452
Reg 0x452[10:8] will control LED_1 as follows

0h = pwr_seq_done
1h = loc_wake_req from analog
2h = loc_wake_req to PHY control
3h = tx_lps_done
4h = tx_lps_done_64
5h = tx_lps
6h = pcs rx sm - receiving
7h = pcs tx sm - tx_enable
13led_0_gpio_ctrl_3R/W0h MSB of LED_0 gpio control. This bit provides additional options for configuring LED_0
If set to 1, it changes the effect of led_0_gpio_ctrl bits of 0x452
Reg 0x452[2:0] will control LED_0 as follows

0h = pwr_seq_done
1h = loc_wake_req from analog
2h = loc_wake_req to PHY control
3h = tx_lps_done
4h = tx_lps_done_64
5h = tx_lps
6h = pcs rx sm - receiving
7h = pcs tx sm - tx_enable
12-9RESERVEDR0h Reserved
8led_2_drv_enR/W0h
0h = LED_2 is in normal operation mode
1h = Drive the value of LED_2 (driven value is bit 7)
7led_2_drv_valR/W0h If bit #8 is set, this is the value of LED_2 Note: There is no LED_2, only if CLK_OUT is configured as LED_2
6led_2_polarityR/W1h LED_2 polarity. Note: There is no LED_2, only if CLK_OUT is configured as LED_2
0h = Active low
1h = Active high
5led_1_drv_enR/W0h Note: There is no LED_2, only if CLK_OUT is configured as LED_2
0h = LED_1 is in normal operation mode
1h = Drive the value of LED_1 (driven value is bit #4)
4led_1_drv_valR/W0h If bit #5 is set, this is the value of LED_1
3led_1_polarityR/W1h LED_1 polarity: if(RX_D3_strap == 1) reset_val = ~CLKOUT_strap else reset_val = ~LED_1_strap
0h = Active low
1h = Active high
2led_0_drv_enR/W0h 0 - LED_0 is in normal operation mode 1 - Drive the value of LED_0 (driven value is bit #1)
1led_0_drv_valR/W0h If bit #2 is set, this is the value of LED_1
0led_0_polarityR/W1h LED_0 polarity: reset_val = ~LED_0_strap
0h = Active low
1h = Active high

7.6.2.44 IO_MUX_CFG_1 Register (Offset = 452h) [Reset = 0000h]

IO_MUX_CFG_1 is shown in Table 7-73.

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Table 7-73 IO_MUX_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
15led_1_clk_div_2_enR/W0h If led_1_gpio is configured to led_1_clk_source, Selects divide by 2 of clock at led_1_clk_source
14-12led_1_clk_sourceR/W0h In case clk_out is MUXed to LED_1 IO, this field controls clk_out source:
000b - XI clock
001b - 200M pll clock
010b - 67MHz ADC clock (recovered)
011b - Free 200MHz clock
100b - 25M MII clock derived from 200M LD clock
101b - 25MHz clock to PLL (XI or XI/2) or POR clock
110b - Core 100MHz clock
111b - 67MHz DSP clock (recovered, 1/3 duty cycle)
11led_1_clk_inv_enR/W0h If led_1_gpio is configured to led_1_clk_source, Selects inversion of clock at led_1_clk_source
10-8led_1_gpio_ctrlR/W0h controls the output of LED_1 IO:
000b - LED_1 (default: LINK + ACT)
001b - LED_1 Clock mux out
010b - WoL
011b - Under-Voltage indication
100b - 1588 TX
101b - 1588 RX
110b - ESD
111b - interrupt

if(RX_D3_strap ==1)
reset_val = 3'b001
else
reset_val = 3'b000
7led_0_clk_div_2_enR/W0h If led_0_gpio is configured to led_0_clk_source, Selects divide by 2 of clock at led_0_clk_source
6-4led_0_clk_sourceR/W0h In case clk_out is MUXed to LED_0 IO, this field controls clk_out source:
0h = XI clock
1h = 200M pll clock
2h = 67MHz ADC clock (recovered)
3h = Free 200MHz clock
4h = 25M MII clock derived from 200M LD clock
5h = 25MHz clock to PLL (XI or XI/2) or POR clock
6h = Core 100MHz clock
7h = 67MHz DSP clock (recovered, 1/3 duty cycle)
3led_0_clk_inv_enR/W0h If led_0_gpio is configured to led_0_clk_source, Selects inversion of clock at led_0_clk_source
2-0led_0_gpio_ctrlR/W0h controls the output of LED_0 IO:
0h = LED_0 (default: LINK) 001b =LED_0 Clock mux out 010b = WoL 011b = Under-Voltage indication 100b = 1588 TX 101b = 1588 RX 110b = ESD 111b = interrupt

7.6.2.45 IO_MUX_CFG_2 Register (Offset = 453h) [Reset = 0001h]

IO_MUX_CFG_2 is shown in Table 7-74.

Return to the Summary Table.

Table 7-74 IO_MUX_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
15cfg_tx_er_on_led1R/W0h configures led_1 pin to tx_er pin and LED_1 pin is made input
14-9RESERVEDR0h Reserved
8clk_o_clk_div_2_enR/W0h If clk_out is configured to output clk_o_clk_source, Selects divide by 2 of clock at clk_o_clk_source
7-4clk_o_clk_sourceR/W0h In case clk_out is MUXed to CLK_O IO, this field controls clk_out source: 0000b - XI clock
0001b - 200M pll clock
0010b - 67MHz ADC clock (recovered)
0011b - Free 200MHz clock
0100b - 25M MII clock derived from 200M LD clock
0101b - 25MHz clock to PLL (XI or XI/2) or POR clock
0110b - Core 100MHz clock
0111b - 67MHz DSP clock (recovered, 1/3 duty cycle)
1000b - CLK25_50 (50MHz in RMII, 25MHz in others)
1001b - 50M RMII RX clk
1010b - SGMII serlz clk
1011b - SGMII deserlz clk
1100b - 30ns tick
1101b - 40ns tick
1110b - DLL TX CLK
1111b - DLL RX CLK
3clk_o_clk_inv_enR/W0h If clk_out is configured to output clk_o_clk_source, Selects inversion of clock at clk_o_clk_source
2-0clk_o_gpio_ctrlR/W1h controls the output of CLK_O IO:
000b - LED_1
001b - CLKOUT Clock mux out
010b - WoL
011b - Under-Voltage indication
100b - 1588 TX
101b - 1588 RX
110b - ESD
111b - interrupt
Automatically gets configured
to 3 'h0 if pin6(LED_1) is strapped
As daisy chain CLKOUT

if(RX_D3_strap ==1)
reset_val = 3'b000
else
reset_val = 3'b001

7.6.2.46 IO_MUX_CFG Register (Offset = 456h) [Reset = 0000h]

IO_MUX_CFG is shown in Table 7-75.

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Table 7-75 IO_MUX_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-14rx_pins_pupd_valueR/W0h when RX pins PUPD force control is enabled, PUPD is contolled by this register
0h = No pull
1h = Pull up
2h = Pull down
3h = Reserved
13rx_pins_pupd_force_controlR/W0h enables PUPD force control on RX MAC pins
0h = No force control
1h = enables force control
12-11tx_pins_pupd_valueR/W0h when TX pins PUPD force control is enabled, PUPD is contolled by this register
0h = No pull
1h = Pull up
2h = Pull down
3h = Reserved
10tx_pins_pupd_force_controlR/W0h enables PUPD force control on TX MAC pins
0h = No force control
1h = enables force control
9-5mac_rx_impedance_ctrlR/W0h This bit control the IO slew rate of the RX MAC interface pads in MII, RGMII, and RMII mode.
00000b - Fast Mode (Default)
00001b - Slow Mode
4-0mac_tx_impedance_ctrlR/W0h This bit adjusts the slew rate of TX_CLK in MII mode.
00000b - Fast Mode (Default)
00001b - Slow Mode

7.6.2.47 IO_STATUS_1 Register (Offset = 457h) [Reset = 0000h]

IO_STATUS_1 is shown in Table 7-76.

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Table 7-76 IO_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0io_status_1R0h If IO direction is controlled via register IO_MUX_CFG & IO_INPUT_MODE_1, and direction is INPUT
(i.e. io_oe_n_force_ctrl=1, io_input_mode[*]=1) - shows the current value of the following IOs:
bit 0 - RX_D3
bit 1 - TX_CLK
bit 2 - TX_EN
bit 3 - TX_D0
bit 4 - TX_D1
bit 5 - TX_D2
bit 6 - TX_D3
bit 7 - INT_N
bit 8 - CLKOUT
bit 9 - LED_0
bit 10 - RX_CLK
bit 11 - RX_DV
bit 12 - 0
bit 13 - RX_ERR
bit 14 - LED_1
bit 15 - RX_D0

7.6.2.48 IO_STATUS_2 Register (Offset = 458h) [Reset = 0000h]

IO_STATUS_2 is shown in Table 7-77.

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Table 7-77 IO_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1-0io_status_2R0h "If IO direction is controlled via register IO_MUX_CFG & IO_INPUT_MODE_2, and direction is INPUT (i.e. io_oe_n_force_ctrl=1, io_input_mode[*]=1) - shows the current value of the following IOs: bit 0 - RX_D1 bit 1 - RX_D2 "

7.6.2.49 CHIP_SOR_1 Register (Offset = 45Dh) [Reset = 0000h]

CHIP_SOR_1 is shown in Table 7-78.

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Table 7-78 CHIP_SOR_1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h
14RESERVEDR0h Reserved
13LED1_PORR0h LED_1 strap sampled at power up
12RX_D3_PORR0h RX_D3 strap sampled at power up
11RESERVEDR0h Reserved
10RESERVEDR0h Reserved
9LED0_STRAPR0h LED_0 strap sampled at power up or reset
8RXD3_STRAPR0h RX_D3 strap sampled at reset
7RXD2_STRAPR0h RX_D2 strap sampled at power up or reset
6RXD1_STRAPR0h RX_D1 strap sampled at power up or reset
5RXD0_STRAPR0h RX_D0 strap sampled at power up or reset
4RXCLK_STRAPR0h RX_CLK strap sampled at power up or reset
3-2RXER_STRAPR0h RX_ER strap sampled at power up or reset
1-0RXDV_STRAPR0h RX_DV strap sampled at power up or reset

7.6.2.50 LED1_CLKOUT_ANA_CTRL Register (Offset = 45Fh) [Reset = 000Ch]

LED1_CLKOUT_ANA_CTRL is shown in Table 7-79.

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Table 7-79 LED1_CLKOUT_ANA_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13-5RESERVEDR0h Reserved
4clkout_ana_sel_1p0v_slR/W0h For selecting test line b/w analog test clocks
3-2led_1_ana_mux_ctrlR/W3h Selects the signal to be sent out on LED_1 pin Automatically selects output from digital if Pin6(LED_1) is strapped As daisy chain CLKOUT if(RX_D3_strap == 1) reset_val = 2'b00 else reset_val = 2'b11
0h = Daisy chain clock
1h = TX_TCLK for test modes
2h = ANA Test clock
3h = clkout_out_1p0v_sl from digital
1-0clkout_ana_mux_ctrlR/W0h Selects the signal to be sent out on CLKOUT pin Automatically selects output from digital if Pin6(LED_1) is strapped As daisy chain CLKOUT if(RX_D3_strap == 1) reset_val = 2'b11 else reset_val = 2'b00
0h = Daisy chain clock
1h = TX_TCLK for test modes
2h = ANA Test clock
3h = clkout_out_1p0v_sl from digital

7.6.2.51 PCS_CTRL_1 Register (Offset = 485h) [Reset = 1078h]

PCS_CTRL_1 is shown in Table 7-80.

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Table 7-80 PCS_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0h Reserved
14cfg_force_slave_phase1_doneR/W0h Force to say phase1 of DSP slave training done
13cfg_dis_ipg_scr_lock_checkR/W0h Disable scrambler lock check during IPG
11-9RESERVEDR0h Reserved
8-0cfg_desc_first_lock_countR/W78h Number of idle symbols to decide on scrambler lock

7.6.2.52 PCS_CTRL_2 Register (Offset = 486h) [Reset = 0A05h]

PCS_CTRL_2 is shown in Table 7-81.

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Table 7-81 PCS_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-8cfg_desc_error_countR/WAh Number of non-idle ymbols to look for to say scrambler unlocked
7-5RESERVEDR0h Reserved
4-0cfg_rem_rcvr_sts_error_cntR/W5h No of error symbols to rem rcvr status to go low

7.6.2.53 TX_INTER_CFG Register (Offset = 489h) [Reset = 0001h]

TX_INTER_CFG is shown in Table 7-82.

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Table 7-82 TX_INTER_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDR0h Reserved
2cfg_force_tx_interleaveR/W0h Force interleave on Tx
1cfg_tx_interleave_enR/W0h Enable interleave on tx, if interleave detected on the Rx
0h = Interleave on Tx disabled
1h = Interleave on Tx enabled if interleave detected on Rx
0cfg_interleave_det_enR/W1h Enable interleave detection
0h = Disable Interleave Detection
1h = Enable Interleave Detection

7.6.2.54 JABBER_CFG Register (Offset = 496h) [Reset = 044Ch]

JABBER_CFG is shown in Table 7-83.

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Table 7-83 JABBER_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10-0cfg_rcv_jab_timer_valR/W44Ch Jabber timeout count in usec

7.6.2.55 TEST_MODE_CTRL Register (Offset = 497h) [Reset = 01C0h]

TEST_MODE_CTRL is shown in Table 7-84.

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Table 7-84 TEST_MODE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0h Reserved
9-4cfg_test_mode1_symbol_cntR/W1Ch number of +1/-1 symbols to send in test_mode_1 N= 2 + 2* CFG_TEST_MODE1_SYMBOL_CNT
3-0RESERVEDR0h Reserved

7.6.2.56 RXF_CFG Register (Offset = 4A0h) [Reset = 1000h]

RXF_CFG is shown in Table 7-85.

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Table 7-85 RXF_CFG Register Field Descriptions
BitFieldTypeResetDescription
15-14bits_nibbles_swapR/W0h Option to swap bits / nibbles inside every RX data byte
0h = regular order, no swaps - RXD[3-0]
1h = swap bits order - RXD[0-3]
Ah = swap nibbles order - { RXD[3-0] , RXD[7-4] }
Bh = swap bits order in each nibble - { RXD[4-7] , RXD[0-3] }
13sfd_byteR/W0h 0 - SFD is 0xD5 (i.e. RXF module searchs 0xD5) 1 - SFD is 0x5D (i.e. RXF module searchs 0x5D)
0h = SFD is 0xD5 (i.e. RXF module searchs 0xD5)
1h = SFD is 0x5D (i.e. RXF module searchs 0x5D)
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10-9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7enhanced_mac_supportR/W0h Enables enhanced RX features. This bit shall be set when using wakeup abilities, CRC check or RX 1588 indication
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3RESERVEDR/W0h Reserved
2RESERVEDR/W0h Reserved
1RESERVEDR0h Reserved
0RESERVEDR/W0h Reserved

7.6.2.57 PG_REG_4 Register (Offset = 553h) [Reset = 0000h]

PG_REG_4 is shown in Table 7-86.

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Table 7-86 PG_REG_4 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR/W0h Reserved
13force_pol_enR/W0h Enable force on polarity
0h = Auto-polarity on MDI
1h = Force polarity on MDI
12force_pol_valR/W0h Polarity force value. Only valid if bit [13] is 1.
0h = Forced Normal polarity
1h = Forced Inverted polarity
11-0RESERVEDR/W0h Reserved

7.6.2.58 TC1_CFG_RW Register (Offset = 560h) [Reset = 07E4h]

TC1_CFG_RW is shown in Table 7-87.

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Table 7-87 TC1_CFG_RW Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0h Reserved
13RESERVEDR/W0h Reserved
4-3cfg_comm_timer_thrsR/W0h selects the hysteresis timer value for TC1 comm ready
0h = 2ms
1h = 500us
2h = 1ms
3h = 4ms
2-0cfg_bad_sqi_thrsR/W4h SQI threshold used to increment Link Failure Count defined by TC1. Whenever SQI becomes worse than the threshold, link failure count (Register 0x0561 bit[9:0]) as defined by TC1 is incremented

TC1_LINK_FAIL_LOSS is shown in Table 7-88.

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Table 7-88 TC1_LINK_FAIL_LOSS Register Field Descriptions

TC1_LINK_TRAINING_TIME is shown in Table 7-89.

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Table 7-89 TC1_LINK_TRAINING_TIME Register Field Descriptions

7.6.2.61 RGMII_CTRL Register (Offset = 600h) [Reset = 0030h]

RGMII_CTRL is shown in Table 7-90.

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Table 7-90 RGMII_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR0h Reserved
6-4rgmii_tx_half_full_thR/W3h RGMII TX sync FIFO half full threshold in number if nibbles
3cfg_rgmii_enR/W0h RGMII enable bit Default from strap if(RX_D2_strap == 1) reset_val = 1 else reset_val = 0
0h = RGMII disable
1h = RGMII enable
2inv_rgmii_txdR/W0h Invert RGMII Tx wire order - full swap [3:0] -- [0:3]
1inv_rgmii_rxdR/W0h Invert RGMII Rx wire order - full swap [3:0] -- [0:3]
0sup_tx_err_fd_rgmiiR/W0h this bit can disable the TX_ERR indication input

7.6.2.62 RGMII_FIFO_STATUS Register (Offset = 601h) [Reset = 0000h]

RGMII_FIFO_STATUS is shown in Table 7-91.

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Table 7-91 RGMII_FIFO_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1rgmii_tx_af_full_errR0h RGMII Tx fifo full error
0rgmii_tx_af_empty_errR0h RGMII Tx fifo empty error

7.6.2.63 RGMII_CLK_SHIFT_CTRL Register (Offset = 602h) [Reset = 0000h]

RGMII_CLK_SHIFT_CTRL is shown in Table 7-92.

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Table 7-92 RGMII_CLK_SHIFT_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1cfg_rgmii_rx_clk_shift_selR/W0h 0: clock and data are aligned 1: clock on PIN is delayed by 2ns relative to RGMII_RX data if({RX_D2_strap, RX_D1_strap} == 2'b11) reset_val = 1 else resett_val = 0
0h = clock and data are aligned
1h = clock on PIN is delayed by 2ns relative to RGMII_RX data
0cfg_rgmii_tx_clk_shift_selR/W0h use this mode when RGMII_TX_CLK & RGMII_TXD are aligned if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b101) reset_val = 1 else if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b110) reset_val = 1 else reset_val = 0

7.6.2.64 SGMII_CTRL_1 Register (Offset = 608h) [Reset = 007Bh]

SGMII_CTRL_1 is shown in Table 7-93.

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Table 7-93 SGMII_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15sgmii_tx_err_disR/W0h SGMII TX err disable bit
14cfg_align_idx_force_enR/W0h Force word boundray index selection
13-10cfg_align_idx_valueR/W0h when cfg_align_idx_force is set,This value set the iword boundray index
9cfg_sgmii_enR/W0h SGMII enable bit Default from strap if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b000) reset_val = 1 else reset_val = 0
0h = SGMII MAC i/f disabled
1h = SGMII MAC i/f enabled
8cfg_sgmii_rx_pol_invertR/W0h SGMII RX bus invert polarity
7cfg_sgmii_tx_pol_invertR/W0h SGMII TX bus invert polarity
6-5serdes_tx_bits_orderR/W3h SERDES TX bits order (input to digital core)
4serdes_rx_bits_orderR/W1h SERDES RX bits order (output of digital core) : 0 - MSB-first (default) 1 - LSB-first (reversed order)
3cfg_sgmii_align_pkt_enR/W1h For aligning the start of read out TX packet (towards serializer) w/ tx_even pulse. To sync with the Code_Group/OSET FSM code slots. Default is '1', when using '0' we go back to Gemini code
2-1sgmii_autoneg_timerR/W1h Selects duration of SGMII Auto-Negotiation timer
0h = 1.6ms
1h = 2us
2h = 800us
3h = 11ms
0sgmii_autoneg_enR/W1h sgmii auto negotiation enable
0h = SGMII autoneg disabled
1h = SGMII autoneg enabled

7.6.2.65 SGMII_STATUS Register (Offset = 60Ah) [Reset = 0000h]

SGMII_STATUS is shown in Table 7-94.

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Table 7-94 SGMII_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12sgmii_page_receivedR0h Clear on read bit. Indicates that a new auto neg page was received
10sgmii_autoneg_completeR0h sgmii autoneg complete indication
0h = SGMII autoneg incomplete
1h = SGMII autoneg completed
9cfg_align_enR0h word boundary FSM - align indication
8cfg_sync_statusR0h word boundary FSM - sync status indication
7-4cfg_align_idxR0h word boundary index selection
3-0RESERVEDR0h Reserved

7.6.2.66 SGMII_CTRL_2 Register (Offset = 60Ch) [Reset = 0024h]

SGMII_CTRL_2 is shown in Table 7-95.

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Table 7-95 SGMII_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0h Reserved
8sgmii_cdr_lock_force_valR/W0h SGMII cdr lock force value
7sgmii_cdr_lock_force_ctrlR/W0h SGMII cdr lock force enable
6sgmii_mr_restart_anRH/W1S0h Restart sgmii autonegotiation
5-3tx_half_full_thR/W4h SGMII TX sync FIFO half full threshold
2-0rx_half_full_thR/W4h SGMII RX sync FIFO half full threshold

7.6.2.67 SGMII_FIFO_STATUS Register (Offset = 60Dh) [Reset = 0000h]

SGMII_FIFO_STATUS is shown in Table 7-96.

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Table 7-96 SGMII_FIFO_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0h Reserved
3sgmii_rx_af_full_errH0h SGMII RX fifo full error
0h = No error indication
1h = SGMII RX fifo full error has been indicated
2sgmii_rx_af_empty_errH0h SGMII RX fifo empty error
0h = No error indication
1h = SGMII RX fifo empty error has been indicated
1sgmii_tx_af_full_errH0h SGMII TX fifo full error
0h = No error indication
1h = SGMII TX fifo full error has been indicated
0sgmii_tx_af_empty_errH0h SGMII TX fiff empty error
0h = No error indication
1h = SGMII TX fifo empty error has been indicated

7.6.2.68 PRBS_STATUS_1 Register (Offset = 618h) [Reset = 0000h]

PRBS_STATUS_1 is shown in Table 7-97.

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Table 7-97 PRBS_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0h Reserved
7-0prbs_err_ov_cntR0h Holds number of error counter overflow that received by the PRBS checker. Value in this register is locked when write is done to register 0x001B bit[0] or bit[1]. Counter stops on 0xFF. Note: when PRBS counters work in single mode, overflow counter is not active

7.6.2.69 PRBS_CTRL_1 Register (Offset = 619h) [Reset = 0574h]

PRBS_CTRL_1 is shown in Table 7-98.

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Table 7-98 PRBS_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0h Reserved
13cfg_pkt_gen_64R/W0h
0h = Transmit 1518 byte packets in packet generation mode
1h = Transmit 64 byte packets in packet generation mode
12send_pktRH/W1S0h Enables generating MAC packet with fix/incremental data w CRC (pkt_gen_en has to be set and cfg_pkt_gen_prbs has to be clear) Cleared automatically when pkt_done is set
11RESERVEDR0h Reserved
10-8cfg_prbs_chk_selR/W5h 000 : Checker receives from RGMII TX
001 : Checker receives from SGMII TX
010 : Checker receives from RMII RX
011 : Checker receives from MII
101 : Checker receives from Cu RX
110 : Reserved
111 : Reserved
7RESERVEDR0h Reserved
6-4cfg_prbs_gen_selR/W7h 000 : PRBS transmits to RGMII RX
001 : PRBS transmits to SGMII RX
010 : PRBS transmits to RMII RX
011 : PRBS transmits to MII RX
101 : PRBS transmits to Cu TX
110 : Reserved
111 : Reserved
3cfg_prbs_cnt_modeR/W0h
0h = Single mode, When one of the PRBS counters reaches max value, PRBS checker stops counting.
1h = Continuous mode, when one of the PRBS counters reaches max value, pulse is generated and counter starts counting from zero again
2cfg_prbs_chk_enableR/W1h Enable PRBS checker
1cfg_pkt_gen_prbsR/W0h If set: (1) When pkt_gen_en is set, PRBS packets are generated continuously (3) When pkt_gen_en is cleared, PRBS RX checker is still enabled If cleared: (1) When pkt_gen_en is set, non - PRBS packet is generated (3) When pkt_gen_en is cleared, PRBS RX checker is disabled as well
0pkt_gen_enR/W0h Enable/disable for prbs/packet generator
0h = Disable for prbs/packet generator
1h = Enable for prbs/packet generator

7.6.2.70 PRBS_CTRL_2 Register (Offset = 61Ah) [Reset = 05DCh]

PRBS_CTRL_2 is shown in Table 7-99.

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Table 7-99 PRBS_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0cfg_pkt_len_prbsR/W5DCh Length (in bytes) of PRBS packets and MAC packets w CRC

7.6.2.71 PRBS_CTRL_3 Register (Offset = 61Bh) [Reset = 007Dh]

PRBS_CTRL_3 is shown in Table 7-100.

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Table 7-100 PRBS_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0h Reserved
7-0cfg_ipg_lenR/W7Dh Inter-packet gap (in bytes) between packets

7.6.2.72 PRBS_STATUS_2 Register (Offset = 61Ch) [Reset = 0000h]

PRBS_STATUS_2 is shown in Table 7-101.

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Table 7-101 PRBS_STATUS_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0prbs_byte_cntR0h Holds number of total bytes that received by the PRBS checker. Value in this register is locked when write is done to register 0x001B bit[0] or bit[1]. When PRBS Count Mode set to zero, count stops on 0xFFFF

7.6.2.73 PRBS_STATUS_3 Register (Offset = 61Dh) [Reset = 0000h]

PRBS_STATUS_3 is shown in Table 7-102.

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Table 7-102 PRBS_STATUS_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0prbs_pkt_cnt_15_0R0h Bits [15:0] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register 0x001B bit[15] or bit[14]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.74 PRBS_STATUS_4 Register (Offset = 61Eh) [Reset = 0000h]

PRBS_STATUS_4 is shown in Table 7-103.

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Table 7-103 PRBS_STATUS_4 Register Field Descriptions
BitFieldTypeResetDescription
15-0prbs_pkt_cnt_31_16R0h Bits [31:16] of number of total packets received by the PRBS checker Value in this register is locked when write is done to register 0x001B bit[15] or bit[14]. When PRBS Count Mode set to zero, count stops on 0xFFFFFFFF

7.6.2.75 PRBS_STATUS_5 Register (Offset = 620h) [Reset = 0000h]

PRBS_STATUS_5 is shown in Table 7-104.

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Table 7-104 PRBS_STATUS_5 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h Reserved
12pkt_doneR0h Set when all MAC packets w CRC are transmitted
11pkt_gen_busyR0h status of packet generator
10prbs_pkt_ovR0h If set, packet counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit[15] of 0x001B
9prbs_byte_ovR0h If set, bytes counter reached overflow Overflow is cleared when PRBS counters are cleared - done by setting bit[15] of 0x001B
8prbs_lockR0h prbs lock status
7-0prbs_err_cntR0h Holds number of errored bytes that received by the PRBS checker Value in this register is locked when write is done to bit[0] or bit[1] When PRBS Count Mode set to zero, count stops on 0xFF Notes: Writing bit 0 generates a lock signal for the PRBS counters. Writing bit 1 generates a lock and clear signal for the PRBS counters

7.6.2.76 PRBS_STATUS_6 Register (Offset = 622h) [Reset = 0000h]

PRBS_STATUS_6 is shown in Table 7-105.

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Table 7-105 PRBS_STATUS_6 Register Field Descriptions
BitFieldTypeResetDescription
15-0pkt_err_cnt_15_0R0h bits [15:0] of counter which records number or PRBS erroneous bytes received. This field gets cleared when bit[15] or bit[14] is written as 1 to register 0x001B

7.6.2.77 PRBS_STATUS_7 Register (Offset = 623h) [Reset = 0000h]

PRBS_STATUS_7 is shown in Table 7-106.

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Table 7-106 PRBS_STATUS_7 Register Field Descriptions
BitFieldTypeResetDescription
15-0pkt_err_cnt_31_16R0h bits [31:16] of counter which records number or PRBS erroneous bytes received. This field gets cleared when bit[15] or bit[14] is written as 1 to register 0x001B

7.6.2.78 PRBS_CTRL_4 Register (Offset = 624h) [Reset = 5511h]

PRBS_CTRL_4 is shown in Table 7-107.

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Table 7-107 PRBS_CTRL_4 Register Field Descriptions
BitFieldTypeResetDescription
15-8cfg_pkt_dataR/W55h Fixed data to be sent in Fix data mode
7-6cfg_pkt_modeR/W0h Selects the type of data sent
0h = Incremental Data
1h = Fixed Data
2h = PRBS Data (Random Data)
3h = PRBS Data (Random Data)
5-3cfg_pattern_vld_bytesR/W2h Number of bytes of valid pattern in packet (Max - 6)
2-0cfg_pkt_cntR/W1h Configures the number of MAC packets to be transmitted by packet generator
0h = 1 packet
1h = 10 packets
2h = 100 packets
3h = 1000 packets
4h = 10000 packets
5h = 100000 packets
6h = 1000000 packets
7h = Continuous packets

7.6.2.79 PATTERN_CTRL_1 Register (Offset = 625h) [Reset = 0000h]

PATTERN_CTRL_1 is shown in Table 7-108.

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Table 7-108 PATTERN_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0pattern_15_0R/W0h Bits 15:0 of pattern

7.6.2.80 PATTERN_CTRL_2 Register (Offset = 626h) [Reset = 0000h]

PATTERN_CTRL_2 is shown in Table 7-109.

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Table 7-109 PATTERN_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0pattern_31_16R/W0h Bits 31:16 of pattern

7.6.2.81 PATTERN_CTRL_3 Register (Offset = 627h) [Reset = 0000h]

PATTERN_CTRL_3 is shown in Table 7-110.

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Table 7-110 PATTERN_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0pattern_47_32R/W0h Bits 47:32 of pattern

7.6.2.82 PMATCH_CTRL_1 Register (Offset = 628h) [Reset = 0000h]

PMATCH_CTRL_1 is shown in Table 7-111.

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Table 7-111 PMATCH_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0pmatch_data_15_0R/W0h Bits 15:0 of Perfect Match Data - used for DA (destination address) match

7.6.2.83 PMATCH_CTRL_2 Register (Offset = 629h) [Reset = 0000h]

PMATCH_CTRL_2 is shown in Table 7-112.

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Table 7-112 PMATCH_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0pmatch_data_31_16R/W0h Bits 31:16 of Perfect Match Data - used for DA (destination address) match

7.6.2.84 PMATCH_CTRL_3 Register (Offset = 62Ah) [Reset = 0000h]

PMATCH_CTRL_3 is shown in Table 7-113.

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Table 7-113 PMATCH_CTRL_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0pmatch_data_47_32R/W0h Bits 47:32 of Perfect Match Data - used for DA (destination address) match

7.6.2.85 TX_PKT_CNT_1 Register (Offset = 639h) [Reset = 0000h]

TX_PKT_CNT_1 is shown in Table 7-114.

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Table 7-114 TX_PKT_CNT_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0tx_pkt_cnt_15_0RC0h Lower 16 bits of Tx packet counter Note : Register is cleared when 0x639, 0x63A, 0x63B are read in sequence

7.6.2.86 TX_PKT_CNT_2 Register (Offset = 63Ah) [Reset = 0000h]

TX_PKT_CNT_2 is shown in Table 7-115.

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Table 7-115 TX_PKT_CNT_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0tx_pkt_cnt_31_16RC0h Upper 16 bits of Tx packet counter Note : Register is cleared when 0x639, 0x63A, 0x63B are read in sequence

7.6.2.87 TX_PKT_CNT_3 Register (Offset = 63Bh) [Reset = 0000h]

TX_PKT_CNT_3 is shown in Table 7-116.

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Table 7-116 TX_PKT_CNT_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0tx_err_pkt_cntRC0h Tx packet w error (CRC error) counter Note : Register is cleared when 0x639, 0x63A, 0x63B are read in sequence

7.6.2.88 RX_PKT_CNT_1 Register (Offset = 63Ch) [Reset = 0000h]

RX_PKT_CNT_1 is shown in Table 7-117.

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Table 7-117 RX_PKT_CNT_1 Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_pkt_cnt_15_0RC0h Lower 16 bits of Rx packet counter Note : Register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

7.6.2.89 RX_PKT_CNT_2 Register (Offset = 63Dh) [Reset = 0000h]

RX_PKT_CNT_2 is shown in Table 7-118.

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Table 7-118 RX_PKT_CNT_2 Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_pkt_cnt_31_16RC0h Upper 16 bits of Rx packet counter Note : Register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

7.6.2.90 RX_PKT_CNT_3 Register (Offset = 63Eh) [Reset = 0000h]

RX_PKT_CNT_3 is shown in Table 7-119.

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Table 7-119 RX_PKT_CNT_3 Register Field Descriptions
BitFieldTypeResetDescription
15-0rx_err_pkt_cntRC0h Rx packet w error (CRC error) counter Note : Register is cleared when 0x63C, 0x63D, 0x63E are read in sequence

7.6.2.91 RMII_CTRL_1 Register (Offset = 648h) [Reset = 0120h]

RMII_CTRL_1 is shown in Table 7-120.

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Table 7-120 RMII_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10cfg_rmii_dis_delayed_txd_enR/W0h If set, disables delay of TXD in RMII mode
9-7cfg_rmii_half_full_thR/W2h FIFO Half Full Threshold in nibbles for the RMII Rx FIFO
6cfg_rmii_modeR/W0h 1 = RMII enabled 0 = RMII disabled if({RX_D2_strap, RX_D1_strap} == 2'b01) reset_val = 1 else reset_val = 0
0h = RMII disabled
1h = RMII enabled
5cfg_rmii_bypass_afifo_enR/W1h 1= RMII async fifo bypass enable 0= RMII async fifo not bypassed
0h = RMII async fifo not bypassed
1h = RMII async fifo bypass enable
4cfg_xi_50R/W0h XI sel for RMII mode if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b010) reset_val = 1 else reset_val = 0
3RESERVEDR/W0h Reserved
2RESERVEDR/W0h Reserved
1cfg_rmii_rev1_0R/W0h RMII Rev1.0 enable bit
0cfg_rmii_enhR/W0h RMII enahnced mode enable bit

7.6.2.92 RMII_STATUS_1 Register (Offset = 649h) [Reset = 0000h]

RMII_STATUS_1 is shown in Table 7-121.

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Table 7-121 RMII_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR0h Reserved
1rmii_af_unf_errR0h Clear on read bit RMII fifo undeflow error status
0rmii_af_ovf_errR0h Clear on Read bit RMII fifo overflow status

7.6.2.93 RMII_OVERRIDE_CTRL Register (Offset = 64Ah) [Reset = 0010h]

RMII_OVERRIDE_CTRL is shown in Table 7-122.

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Table 7-122 RMII_OVERRIDE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR0h Reserved
10cfg_clk50_tx_dllR/W0h 1 = use 50M DLL clock in RMII master for TX 0 = legacy mode if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b011) reset_val = 1 else reset_val = 0
0h = legacy mode
1h = use 50M DLL clock in RMII master for TX
9cfg_clk50_dllR/W0h 1 = use 50M DLL clock in RMII slave for RX 0 = use legacy mode if({RX_D2_strap, RX_D1_strap, RX_D0_strap} == 3'b010) reset_val = 1 else reset_val = 0
0h = use legacy mode
1h = use 50M DLL clock in RMII slave for RX
8RESERVEDR/W0h Reserved
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3RESERVEDR/W0h Reserved
2RESERVEDR/W0h Reserved
1RESERVEDR/W0h Reserved
0RESERVEDR/W0h Reserved

7.6.2.94 dsp_reg_71 Register (Offset = 871h) [Reset = 0000h]

dsp_reg_71 is shown in Table 7-123.

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Table 7-123 dsp_reg_71 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0h Reserved
7-5worst_sqi_outRC0h Worst SQI value since last read
4RESERVEDR0h Reserved
3-1sqi_outR0h SQI value
0RESERVEDR0h Reserved

7.6.2.95 MMD1_PMA_CTRL_1 Register (Offset = 1000h) [Reset = 0000h]

MMD1_PMA_CTRL_1 is shown in Table 7-124.

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Table 7-124 MMD1_PMA_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15PMA_resetR/W0h 0 = PMA not reset 1= PMA reset
0h = PMA not reset
1h = PMA reset
14-1RESERVEDR0h Reserved
0PMA_loopbackR/W0h 0 = PMA loopback not set 1= PMA loopback set
0h = PMA loopback not set
1h = PMA loopback set

7.6.2.96 MMD1_PMA_STATUS_1 Register (Offset = 1001h) [Reset = 0000h]

MMD1_PMA_STATUS_1 is shown in Table 7-125.

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Table 7-125 MMD1_PMA_STATUS_1 Register Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDR0h Reserved
1-0RESERVEDR0h Reserved

7.6.2.97 MMD1_PMA_STAUS_2 Register (Offset = 1007h) [Reset = 003Dh]

MMD1_PMA_STAUS_2 is shown in Table 7-126.

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Table 7-126 MMD1_PMA_STAUS_2 Register Field Descriptions
BitFieldTypeResetDescription
15-6RESERVEDR0h Reserved
5-0PMA/PMD type selectionR3Dh PMA or PMD type selection field
11111xb = reserved for future use
111100b = reserved for future use
1110xxb = reserved for future use
110xxxb = reserved for future use
111101b = 100BASE-T1 PMA or PMD

7.6.2.98 MMD1_PMA_EXT_ABILITY_1 Register (Offset = 100Bh) [Reset = 0800h]

MMD1_PMA_EXT_ABILITY_1 is shown in Table 7-127.

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Table 7-127 MMD1_PMA_EXT_ABILITY_1 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11BASE-T1 extended abilitiesR1h 1 = PMA/PMD has BASE-T1 extended abilities listed in register 18 in MMD1 0 = PMA/PMD does not have BASE-T1 extended abilities
0h = PMA/PMD does not have BASE-T1 extended abilities
1h = PMA/PMD has BASE-T1 extended abilities listed in register 18 in MMD1
10-0RESERVEDR0h Reserved

7.6.2.99 MMD1_PMA_EXT_ABILITY_2 Register (Offset = 1012h) [Reset = 0001h]

MMD1_PMA_EXT_ABILITY_2 is shown in Table 7-128.

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Table 7-128 MMD1_PMA_EXT_ABILITY_2 Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0h Reserved
0100BASE-T1 abilityR1h 1 = PMA/PMD is able to perform 100BASE-T1 0 = PMA/PMD is not able to perform 100BASE-T1
0h = PMA/PMD is not able to perform 100BASE-T1
1h = PMA/PMD is able to perform 100BASE-T1

7.6.2.100 MMD1_PMA_CTRL_2 Register (Offset = 1834h) [Reset = 8000h]

MMD1_PMA_CTRL_2 is shown in Table 7-129.

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Table 7-129 MMD1_PMA_CTRL_2 Register Field Descriptions
BitFieldTypeResetDescription
15master_slave_man_cfg_enR1h Value always 1
14brk_ms_cfgR/W0h 1 = Configure PHY as MASTER 0 = Configure PHY as SLAVE pkg_36: reset_val = LED_0_strap pkg_28: reset_val = RX_D3_strap
0h = Configure PHY as SLAVE
1h = Configure PHY as MASTER
13-4RESERVEDR0h Reserved
3-0type selectionR0h type selection field 1xxxb = Reserved for future use 01xxb = Reserved for future use 001xb = Reserved for future use 0001b = Reserved for future use
0h = 100BASE-T1

7.6.2.101 MMD1_PMA_TEST_MODE_CTRL Register (Offset = 1836h) [Reset = 0000h]

MMD1_PMA_TEST_MODE_CTRL is shown in Table 7-130.

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Table 7-130 MMD1_PMA_TEST_MODE_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15-13brk_test_modeR/W0h 100BASE-T1 test mode control
000b = Normal mode operation
001b = Test mode 1
010b = Test mode 2
011b = Reserved
100b = Test mode 4
101b = Test mode 5
110b = Reserved
111b = Reserved
12-0RESERVEDR/W0h Reserved

7.6.2.102 MMD3_PCS_CTRL_1 Register (Offset = 3000h) [Reset = 0000h]

MMD3_PCS_CTRL_1 is shown in Table 7-131.

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Table 7-131 MMD3_PCS_CTRL_1 Register Field Descriptions
BitFieldTypeResetDescription
15PCS_ResetR/W0h Reset bit, Self Clear. When write to this bit 1: 1. reset the registers (not vendor specific) at MMD3/MMD7. 2. Reset brk_top Please notice: This register is WSC (write-self-clear) and not read-only!
14PCS_loopbackR/W0h This bit is cleared by PCS_Reset
13-11RESERVEDR0h Reserved
10rx_clock_stoppableR/W0h RW, reset value = 1. 1= PHY may stop receive clock during LPI 0= Clock not stoppable Note: this flop implemented at glue logic
9-0RESERVEDR0h Reserved

7.6.2.103 MMD3_PCS_Status_1 Register (Offset = 3001h) [Reset = 0000h]

MMD3_PCS_Status_1 is shown in Table 7-132.

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Table 7-132 MMD3_PCS_Status_1 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0h Reserved
11TX_LPI_receivedR0h RO/LH
0h = LPI not received
1h = Tx PCS hs received LPI
10RX_LPI_receivedR0h RO/LH
0h = LPI not received
1h = Rx PCS hs received LPI
9Tx_LPI_indicationR0h 1= TX PCS is currently receiving LPI 0= PCS is not currently receiving LPI
0h = PCS is not currently receiving LPI
1h = TX PCS is currently receiving LPI
8Rx_LPI_indicationR0h 1= RX PCS is currently receiving LPI 0= PCS is not currently receiving LPI
0h = PCS is not currently receiving LPI
1h = RX PCS is currently receiving LPI
7RESERVEDR0h Reserved
6tx_clock_stoppableR0h 1= the MAC may stop the clock during LPI 0= Clock not stoppable
0h = Clock not stoppable
1h = the MAC may stop the clock during LPI
5-0RESERVEDR0h Reserved