DLPS292A July   2025  – December 2025 DLPC8424 , DLPC8444 , DLPC8454

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Compatability Table
  6. 5 Pin Configuration and Functions
    1.     7
    2. 5.1  Initialization, Board Level Test, and Debug
    3. 5.2  V-by-One Interface Input Data and Control
    4. 5.3  FPD-Link Port(s) Input Data and Control
    5. 5.4  DSI Input Data and Clock (Not Supported in DLPC8424, DLPC8444, and DLPC8454)
    6. 5.5  DMD SubLVDS Interface
    7. 5.6  DMD Reset and Low Speed Interfaces
    8. 5.7  Flash Interface
    9. 5.8  Peripheral Interfaces
    10. 5.9  GPIO Peripheral Interface
    11. 5.10 Clock and PLL Support
    12. 5.11 Power and Ground
    13. 5.12 I/O Type Subscript Definition
    14. 5.13 Internal Pullup and Pulldown Characteristics
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2.     23
    3. 6.2  ESD Ratings
    4. 6.3  Recommended Operating Conditions
    5. 6.4  Thermal Information
    6. 6.5  Power Electrical Characteristics
    7. 6.6  Pin Electrical Characteristics
    8. 6.7  DMD SubLVDS Interface Electrical Characteristics
    9.     30
    10. 6.8  DMD Low Speed Interface Electrical Characteristics
    11.     32
    12. 6.9  V-by-One Interface Electrical Characteristics
    13. 6.10 FPD Link LVDS Electrical Characteristics
    14. 6.11 USB Electrical Characteristics
    15.     36
    16. 6.12 System Oscillator Timing Requirements
    17.     38
    18. 6.13 Power Supply and Reset Timing Requirements
    19.     40
    20. 6.14 V-by-One Interface General Timing Requirements
    21.     42
    22. 6.15 FPD Link Interface General Timing Requirements
    23. 6.16 Flash Interface Timing Requirements
    24.     45
    25. 6.17 Source Frame Timing Requirements
    26.     47
    27. 6.18 Synchronous Serial Port Interface Timing Requirements
    28.     49
    29. 6.19 I2C Interface Timing Requirements
    30. 6.20 Programmable Output Clock Timing Requirements
    31. 6.21 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    32.     53
    33. 6.22 DMD Low Speed Interface Timing Requirements
    34.     55
    35. 6.23 DMD SubLVDS Interface Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 V-by-One Interface
      3. 7.3.3 FPD-Link Interface
      4. 7.3.4 DMD (SubLVDS) Interface
      5. 7.3.5 Serial Flash Interface
      6. 7.3.6 GPIO Supported Functionality
        1.       67
        2.       68
      7. 7.3.7 Debug Support
  9. 8 Power Supply Recommendations
    1. 8.1 System Power-Up and Power-Down Sequence
    2. 8.2 DMD Fast Park Control (PARKZ)
    3. 8.3 Power Supply Management
    4. 8.4 Hotplug Usage
    5. 8.5 Power Supplies for Unused Input Source Interfaces
    6. 8.6 Power Supplies
      1. 8.6.1 Power Supplies DLPA3085 or DLPA3082
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Layout Guideline for DLPC8424 or DLPC8444 or DLPC8454 Reference Clock
        1. 9.1.1.1 Recommended Crystal Oscillator Configuration
      2. 9.1.2 V-by-One Interface Layout Considerations
      3. 9.1.3 DMD Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      4. 9.1.4 Power Supply Layout Guidelines
    2. 9.2 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Device Nomenclature
      1. 10.5.1 Device Markings
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
      1. 10.8.1 Video Timing Parameter Definitions
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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7.3.3 FPD-Link Interface

The DLPC84x4 supports two FPD-Link 5-lane ports, which can be configured for single-port use (Port A or Port B), or for dual-port use (Port A and Port B). The third FPD port (Port C) is reserved for parallel port use only. FPD ports A and B support a limited set of remapping options within each port, but there is no remapping between ports. When utilizing this feature, each unique lane pair can only be mapped to one unique destination lane pair, and intralane remapping (that is, swapping P with N) is not supported. In addition, the A and B ports can be swapped. Lane and port remapping (specified in Flash) can help with board layout as needed. The typical lane mapping is shown in Figure 7-3. An example of an alternate lane mapping is shown in Figure 7-4. The specific intraport remapping options available are shown in Table 7-9.


DLPC8424 DLPC8444 DLPC8454 Example of Typical FPD-Link Port Lane Mapping

Figure 7-3 Example of Typical FPD-Link Port Lane Mapping

DLPC8424 DLPC8444 DLPC8454 Example of Alternate FPD-Link Port Lane Mapping

Figure 7-4 Example of Alternate FPD-Link Port Lane Mapping
Table 7-9 FPD-Link Intra Port Data Mapping Options
Mapping Options for Ports A and BInput Data PortInternal Final Data Path
0P2x_LVDS_D0_P/NFPD_x_PA
1P2x_LVDS_D1_P/NFPD_x_PA
2P2x_LVDS_D2_P/NFPD_x_PA
3P2x_LVDS_D3_P/NFPD_x_PA
4P2x_LVDS_D4_P/NFPD_x_PA
4P2x_LVDS_D0_P/NFPD_x_PB
0P2x_LVDS_D1_P/NFPD_x_PB
1P2x_LVDS_D2_P/NFPD_x_PB
2P2x_LVDS_D3_P/NFPD_x_PB
3P2x_LVDS_D4_P/NFPD_x_PB
3P2x_LVDS_D0_P/NFPD_x_PC
4P2x_LVDS_D1_P/NFPD_x_PC
0P2x_LVDS_D2_P/NFPD_x_PC
1P2x_LVDS_D3_P/NFPD_x_PC
2P2x_LVDS_D4_P/NFPD_x_PC
2P2x_LVDS_D0_P/NFPD_x_PD
3P2x_LVDS_D1_P/NFPD_x_PD
4P2x_LVDS_D2_P/NFPD_x_PD
0P2x_LVDS_D3_P/NFPD_x_PD
1P2x_LVDS_D4_P/NFPD_x_PD
1P2x_LVDS_D0_P/NFPD_x_PE
2P2x_LVDS_D1_P/NFPD_x_PE
3P2x_LVDS_D2_P/NFPD_x_PE
4P2x_LVDS_D3_P/NFPD_x_PE
0P2x_LVDS_D4_P/NFPD_x_PE

Independent of the remapping of the physical FPD interface, the DLPC84x4 supports a number of data mappings onto the actual physical interface. There are three different 30-bit data mappings and two different 24-bit data mappings supported. FPD sources must match at least one of these mappings. These are shown in Table 7-10, Table 7-11, Table 7-12, Table 7-13, and Table 7-14.

Table 7-10 FPD-Link Data Mapping onto Physical Interface (30-Bit Mode 0)
Bit Mapping—30-Bit Mode 0(1)
(30 bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2Mapper Output
PA-6G/Y[4]Y[4]A(4)
PA-5R/Cr[9]Cb/Cr[9]B(9)
PA-4R/Cr[8]Cb/Cr[8]B(8)
PA-3R/Cr[7]Cb/Cr[7]B(7)
PA-2R/Cr[6]Cb/Cr[6]B(6)
PA-1R/Cr[5]Cb/Cr[5]B(5)
PA-0R/Cr[4]Cb/Cr[4]B(4)
PB-6B/Cb[5]UnusedC(5)
PB-5B/Cb[4]UnusedC(4)
PB-4G/Y[9]Y[9]A(9)
PB-3G/Y[8]Y[8]A(8)
PB-2G/Y[7]Y[7]A(7)
PB-1G/Y[6]Y[6]A(6)
PB-0G/Y[5]Y[5]A(5)
PC-6Data EnData EnData En
PC-5VSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNC
PC-3B/Cb[9]UnusedC(9)
PC-2B/Cb[8]UnusedC(8)
PC-1B/Cb[7]UnusedC(7)
PC-0B/Cb[6]UnusedC(6)
PD-63D_L/R_Ref3D_L/R_Ref3D_Ref
PD-5B/Cb[3]UnusedC(3)
PD-4B/Cb[2]UnusedC(2)
PD-3G/Y[3]Y[3]A(3)
PD-2G/Y[2]Y[2]A(2)
PD-1R/Cr[3]Cb/Cr[3]B(3)
PD-0R/Cr[2]Cb/Cr[2]B(2)
PE-6FieldFieldField
PE-5B/Cb[1]UnusedC(1)
PE-4B/Cb[0]UnusedC(0)
PE-3G/Y[1]Y[1]A(1)
PE-2G/Y[0]Y[0]A(0)
PE-1R/Cr[1]Cb/Cr[1]B(1)
PE-0R/Cr[0]Cb/Cr[0]B(0)
(1) Input data bits are defined with bit[9] as the most significant bit, and bit[0] as the least significant bit.
Table 7-11 FPD-Link Data Mapping onto Physical Interface (30-Bit Mode 1)
Bit Mapping—30-Bit Mode 1(1)
(30 bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2Mapper Output
PA-6G/Y[2]Y[2]A(2)
PA-5R/Cr[7]Cb/Cr[7]B(7)
PA-4R/Cr[6]Cb/Cr[6]B(6)
PA-3R/Cr(5]Cb/Cr[5]B(5)
PA-2R/Cr[4]Cb/Cr[4]B(4)
PA-1R/Cr[3]Cb/Cr[3]B(3)
PA-0R/Cr[2]Cb/Cr[2]B(2)
PB-6B/Cb[3]UnusedC(3)
PB-5B/Cb[2]UnusedC(2)
PB-4G/Y[7]Y[7]A(7)
PB-3G/Y[6]Y[6]A(6)
PB-2G/Y[5]Y[5]A(5)
PB-1G/Y[4]Y[4]A(4)
PB-0G/Y[3]Y[3]A(3)
PC-6Data EnData EnData En
PC-5VSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNC
PC-3B/Cb[7]UnusedC(7)
PC-2B/Cb[6]UnusedC(6)
PC-1B/Cb[5]UnusedC(5)
PC-0B/Cb[4]UnusedC(4)
PD-63D_L/R_Ref3D_L/R_Ref3D_Ref
PD-5B/Cb[9]UnusedC(9)
PD-4B/Cb[8]UnusedC(8)
PD-3G/Y[9]Y[9]A(9)
PD-2G/Y[8]Y[8]A(8)
PD-1R/Cr[9]Cb/Cr[9]B(9)
PD-0R/Cr[8]Cb/Cr[8]B(8)
PE-6FieldFieldField
PE-5B/Cb[1]UnusedC(1)
PE-4B/Cb[0]UnusedC(0)
PE-3G/Y[1]Y[1]A(1)
PE-2G/Y[0]Y[0]A(0)
PE-1R/Cr[1]Cb/Cr[1]B(1)
PE-0R/Cr[0]Cb/Cr[0]B(0)
(1) Input data bits are defined with bit[9] as the most significant bit, and bit[0] as the least significant bit.
Table 7-12 FPD-Link Data Mapping onto Physical Interface (30-Bit Mode 2)
Bit Mapping—30-Bit Mode 2(1)
(30 bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2Mapper Output
PA-6G/Y[0]Y[0]A(0)
PA-5R/Cr[5]Cb/Cr[5]B(5)
PA-4R/Cr[4]Cb/Cr[4]B(4)
PA-3R/Cr(3]Cb/Cr[3]B(3)
PA-2R/Cr[2]Cb/Cr[2]B(2)
PA-1R/Cr[1]Cb/Cr[1]B(1)
PA-0R/Cr[0]Cb/Cr[0]B(0)
PB-6B/Cb[1]UnusedC(1)
PB-5B/Cb[0]UnusedC(0)
PB-4G/Y[5]Y[5]A(5)
PB-3G/Y[4]Y[4]A(4)
PB-2G/Y[3]Y[3]A(3)
PB-1G/Y[2]Y[2]A(2)
PB-0G/Y[1]Y[1]A(1)
PC-6Data EnData EnData En
PC-5VSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNC
PC-3B/Cb[5]UnusedC(5)
PC-2B/Cb[4]UnusedC(4)
PC-1B/Cb[3]UnusedC(3)
PC-0B/Cb[2]UnusedC(2)
PD-63D_L/R_Ref3D_L/R_Ref3D_Ref
PD-5B/Cb[7]UnusedC(7)
PD-4B/Cb[6]UnusedC(6)
PD-3G/Y[7]Y[7]A(7)
PD-2G/Y[6]Y[6]A(6)
PD-1R/Cr[7]Cb/Cr[7]B(7)
PD-0R/Cr[6]Cb/Cr[6]B(6)
PE-6FieldFieldField
PE-5B/Cb[9]UnusedC(9)
PE-4B/Cb[8]UnusedC(8)
PE-3G/Y[9]Y[9]A(9)
PE-2G/Y[8]Y[8]A(8)
PE-1R/Cr[9]Cb/Cr[9]B(9)
PE-0R/Cr[8]Cb/Cr[8]B(8)
(1) Input data bits are defined with bit[9] as the most significant bit, and bit[0] as the least significant bit.
Table 7-13 FPD-Link Data Mapping onto Physical Interface (24-Bit Mode 0)(1)(2)
Bit Mapping—24-Bit Mode 0(1)
(24 bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2Mapper Output
PA-6G/Y[0]Y[0]A(2)
PA-5R/Cr[5]Cb/Cr[5]B(7)
PA-4R/Cr[4]Cb/Cr[4]B(6)
PA-3R/Cr(3]Cb/Cr[3]B(5)
PA-2R/Cr[2]Cb/Cr[2]B(4)
PA-1R/Cr[1]Cb/Cr[1]B(3)
PA-0R/Cr[0]Cb/Cr[0]B(2)
PB-6B/Cb[1]UnusedC(3)
PB-5B/Cb[0]UnusedC(2)
PB-4G/Y[5]Y[5]A(7)
PB-3G/Y[4]Y[4]A(6)
PB-2G/Y[3]Y[3]A(5)
PB-1G/Y[2]Y[2]A(4)
PB-0G/Y[1]Y[1]A(3)
PC-6Data EnData EnData En
PC-5VSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNC
PC-3B/Cb[5]UnusedC(7)
PC-2B/Cb[4]UnusedC(6)
PC-1B/Cb[3]UnusedC(5)
PC-0B/Cb[2]UnusedC(4)
PD-63D_L/R_Ref or Field3D_L/R_Ref or Field3D_Ref or Field
PD-5B/Cb[7]UnusedC(9)
PD-4B/Cb[6]UnusedC(8)
PD-3G/Y[7]Y[7]A(9)
PD-2G/Y[6]Y[6]A(8)
PD-1R/Cr[7]Cb/Cr[7]B(9)
PD-0R/Cr[6]Cb/Cr[6]B(8)
PE-6UnusedUnusedUnused
PE-5UnusedUnusedUnused
PE-4UnusedUnusedUnused
PE-3UnusedUnusedUnused
PE-2UnusedUnusedUnused
PE-1UnusedUnusedUnused
PE-0UnusedUnusedUnused
(1) To support 24-bit data, the mapper shifts each 8-bit color up by 2 bits, and forces output bits A[1], A[0], B[1], B[0], C[1], and C[0] to value '0'.
(2) Input data bits are defined with bit[7] as the most significant bit, and bit[0] as the least significant bit.
Table 7-14 FPD-Link Data Mapping onto Physical Interface (24-Bit Mode 1) (1)
Bit Mapping—24-Bit Mode 1(1)(2)
(24 bits per pixel)
Mapper InputRGB/YCbCr 4:4:4YCbCr 4:2:2Mapper Output
PA-6G/Y[2]Y[2]A(4)
PA-5R/Cr[7]Cb/Cr[7]B(9)
PA-4R/Cr[6]Cb/Cr[6]B(8)
PA-3R/Cr(5]Cb/Cr[5]B(7)
PA-2R/Cr[4]Cb/Cr[4]B(6)
PA-1R/Cr[3]Cb/Cr[3]B(5)
PA-0R/Cr[2]Cb/Cr[2]B(4)
PB-6B/Cb[3]UnusedC(5)
PB-5B/Cb[2]UnusedC(4)
PB-4G/Y[7]Y[7]A(9)
PB-3G/Y[6]Y[6]A(8)
PB-2G/Y[5]Y[5]A(7)
PB-1G/Y[4]Y[4]A(6)
PB-0G/Y[3]Y[3]A(5)
PC-6Data EnData EnData En
PC-5VSYNCVSYNCVSYNC
PC-4HSYNCHSYNCHSYNC
PC-3B/Cb[7]UnusedC(9)
PC-2B/Cb[6]UnusedC(8)
PC-1B/Cb[5]UnusedC(7)
PC-0B/Cb[4]UnusedC(6)
PD-63D_L/R_Ref or Field3D_L/R_Ref or Field3D_Ref or Field
PD-5B/Cb[1]UnusedC(3)
PD-4B/Cb[0]UnusedC(2)
PD-3G/Y[1]Y[1]A(3)
PD-2G/Y[0]Y[0]A(2)
PD-1R/Cr[1]Cb/Cr[1]B(3)
PD-0R/Cr[0]Cb/Cr[0]B(2)
PE-6UnusedUnusedUnused
PE-5UnusedUnusedUnused
PE-4UnusedUnusedUnused
PE-3UnusedUnusedUnused
PE-2UnusedUnusedUnused
PE-1UnusedUnusedUnused
PE-0UnusedUnusedUnused
(1) To support 24-bit data, the mapper shifts each 8-bit color up by 2 bits, and forces output bits A[1], A[0], B[1], B[0], C[1], and C[0] to value '0'.
(2) Input data bits are defined with bit[7] as the most significant bit, and bit[0] as the least significant bit.