ZHCSCM1F July   2014  – November 2020 DLPC3430 , DLPC3435

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Test Pins and General Control
    2. 5.2 Parallel Port Input
    3. 5.3 DSI Input Data and Clock
    4. 5.4 DMD Reset and Bias Control
    5. 5.5 DMD Sub-LVDS Interface
    6. 5.6 Peripheral Interface
    7. 5.7 GPIO Peripheral Interface
    8. 5.8 Clock and PLL Support
    9. 5.9 Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 DSI Host Timing Requirements
    16. 6.16 Flash Interface Timing Requirements
    17. 6.17 Other Timing Requirements
    18. 6.18 DMD Sub-LVDS Interface Switching Characteristics
    19. 6.19 DMD Parking Switching Characteristics
    20. 6.20 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 PDATA Bus – Parallel Interface Bit Mapping Modes
        4. 7.3.1.4 DSI Interface
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  PLL Power Layout
      2. 10.1.2  Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3  DSI Interface Layout
      4. 10.1.4  Unused Pins
      5. 10.1.5  DMD Control and Sub-LVDS Signals
      6. 10.1.6  Layer Changes
      7. 10.1.7  Stubs
      8. 10.1.8  Terminations
      9. 10.1.9  Routing Vias
      10. 10.1.10 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 静电放电警告
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

4 Revision History

Changes from Revision E (August 2019) to Revision F (November 2020)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • Changed maximum flash size from 64-Mb to 128-Mb Go
  • Changed GPIO_08 (PROJ_ON) pulse width requirement and added a requirement to keep GPIO_08 high until HOST_IRQ goes low Go
  • Changed the package designator description for the DLPC3430 to match the actual packageGo

Changes from Revision D (May 2019) to Revision E (August 2019)

  • 总数据表格式和订购更新Go
  • Deleted mention of mirror parking time from PARKZ pin description and moved to a specification tableGo
  • Changed JTAG pin names from Reserved to proper names Go
  • Deleted support for adjustable DATAEN_CMD polarity Go
  • Deleted mention of a specific 3D command Go
  • Deleted support for adjusting PCLK capture edge in software Go
  • Changed the description of how to use the CMP_OUT pin and corrected how the comparator must use GPIO_10 (RC_CHARGE) instead of CMP_PWM Go
  • Deleted support for CMP_PWMGo
  • Added note about VCC_INTF power up recommendations if secondary devices are on the I2C bus Go
  • Deleted mention of unsupported keypad inputs Go
  • Corrected optional MTR_SENSE support to GPIO_18 instead of GPIO_19 Go
  • Deleted mention of unsupported light sensor on GPIO_13 and GPIO_12 Go
  • Deleted reference of the RC_CHARGE circuit being used for the light sensor and added reference of it being used for the thermistor Go
  • Deleted reference of the LS_PWR circuit being used for the light sensorGo
  • Deleted mention of the unsupported LABB output sample and hold sensor control signalGo
  • Clarified GPIO_03 - GPIO_01 pins are required to be used as a SPI1 portGo
  • Deleted misleading note about GPIO pins defaulting to inputs Go
  • Corrected how pins are mentioned that are only available on the DLPC3435Go
  • Added missing I/O definition 10 Go
  • Deleted unneeded VCC_INTF and VCC_FLSH absolute maximum values Go
  • Added high voltage tolerant note to Absolute Maximum Ratings table Go
  • Changed incorrect pin tolerance Go
  • Changed Power Electrical Characteristics table to reflect updated power measurement values and techniques Go
  • Deleted reference to unsupported IDLE mode Go
  • Added note that the power numbers vary depending on the utilized softwareGo
  • Changed and fixed incorrect test conditions for current drive strengthsGo
  • Deleted redundant ǀVODǀ specification which is referenced in later sectionsGo
  • Added minimum and maximum values for VOH for I/O type 4Go
  • Added minimum and maximum values for VOL for I/O type 4Go
  • Deleted incorrect reference to 2.5V, 24mA drive Go
  • Corrected I2C buffer test conditionsGo
  • Deleted incorrect steady-state common mode voltage reference Go
  • Changed high voltage tolerant I/O note to only refer to the I2C buffer and changed VCC to VCC_INTF.Go
  • Added |VOD| minimum and maximum values, and changed the typical value.Go
  • Added high-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted redundant mention of specification, and changed the typical value. Go
  • Added low-level output voltage minimum and maximum values for the sub-LVDS DMD interface, deleted redundant mention of specification, and changed the typical value. Go
  • Corrected the name of the DMD Low-Speed signals from inputs to outputs. Go
  • Deleted VOH(DC) maximum and VOL(DC) minimum values. Go
  • Added note about DMD input specs being met if a proper series termination resistor is used Go
  • Deleted reference of selecting unsupported oscillator frequency Go
  • Corrected system oscillator clock period to match clock frequency Go
  • Changed pulse duration percent spec from a maximum to a minimum Go
  • Added condition for VDD rise time Go
  • Deleted the incorrect part of the tp_tvb definitionGo
  • Deleted unneeded total horizontal blanking equation Go
  • Changed minimum total vertical blanking equation Go
  • Increased maximum PCLK from 150MHz to 155MHz Go
  • Deleted reference to various signal's active edges being configurable Go
  • Changed the minimum flash SPI_CLK frequencyGo
  • Corrected flash interface clock period to match clock frequency Go
  • Added Section 6.17 section to more clearly list signal transition time requirementsGo
  • Changed DMD HS Clock switching rate from maximum to nominal and added accompanying clock specification Go
  • Added Section 6.19 sectionGo
  • Added the Section 6.20 section to clarify chipset support requirementsGo
  • Changed how chipset support is mentioned in the Detailed Description section Go
  • Increased maximum frame rate from 122 Hz to 242 Hz Go
  • Deleted support for 3D video over DSI Go
  • Deleted reference to internal software tools and clarified how firmware affects the supported resolution and frame rates Go
  • Added note stating bits per pixel limitation at 120 Hz with DSI inputGo
  • Added note that up to four DSI lanes may be required to fully utilize the bandwidth Go
  • Deleted mention of sequencer sync mode as its generally assumed to be autoGo
  • Clarified note about VSYNC_WE needing to remain active Go
  • Deleted support for changing the clock active edge and clarified support of changing the sync active edgeGo
  • Changed the DATAEN_CMD signal to not be optional Go
  • Added note that LP mode is required during vertical time for DSI Go
  • Changed requirement related to DSI initialization Go
  • Deleted incorrect DSI data type; see software programmers guide instead.Go
  • Added information that the parallel interface isn't ready to accept data until the auto-initialization process is completedGo
  • Changed how the 500 ms startup time is described Go
  • Changed SPI flash key timing parameter access frequency minimum and maximum valuesGo
  • Changed maximum flash size supported from 16Mb to 64Mb Go
  • Deleted SPI signal routing section Go
  • Deleted support for a light sensor integrated with the DLPC34xx controller Go
  • Added missing timing definitions Go
  • Clarified that the mentioned SDR clock speed is the typical valueGo
  • Changed how the DMD Sub-LVDS Interface requirements are mentioned Go
  • Deleted DMD Interface stack-up image Go
  • Deleted equation concerning DMD interface system timing margin Go
  • Changed the description of how PROJ_ON affects the power supplies Go
  • Changed which signals are listed as tri-stated at power up and which signals are pulled low Go
  • Changed 1-oz copper plane recommendation Go
  • Deleted reference to unsupported option of variable frequency reference clockGo
  • Added additional DMD data and DMD clock signal matching requirements Go
  • Changed maximum mismatch from ±0.1" to ±1.0" Go
  • Changed incorrect signal matching requirement table noteGo
  • Changed differential signal layer change to a recommendationGo
  • Changed wording requiring no more than two vias on certain DMD signals Go
  • Changed device markings image and definitions Go

Changes from Revision C (July 2016) to Revision D (May 2019)

  • Changed mirror parking time from "500 μs" to "20 ms" for PARKZ description in Pin Functions tableGo
  • Updated mirror parking time from "500 μs" to "20 ms" in Figure 27. DLPC343x Power-Up / PARKZ = 0 Initiated Fast PARK and Power-Down Go

Changes from Revision B (February 2016) to Revision C (July 2016)

Changes from Revision A (January 2016) to Revision B (February 2016)

  • 更新了整篇数据表以显示 DLPC3430 和 DLPC3435 控制器的正确信息，并更正了文本和图片中 DLPC3430 和 DLPC3435 的器件型号Go

Changes from Revision * (July 2014) to Revision A (January 2016)