ZHCSD19A September   2014  – October 2015 DLP9000

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  Timing Requirements
    8. 7.8  Capacitance at Recommended Operating Conditions
    9. 7.9  Typical Characteristics
    10. 7.10 System Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Optical and System Image Quality
    14. 7.14 Window Characteristics
    15. 7.15 Chipset Component Usage Specification
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 DLP9000FLS
      2. 9.4.2 DLP9000XFLS
    5. 9.5 Window Characteristics and Optics
      1. 9.5.1 Optical Interface and System Image Quality
      2. 9.5.2 Numerical Aperture and Stray Light Control
      3. 9.5.3 Pupil Match
      4. 9.5.4 Illumination Overfill
    6. 9.6 Micromirror Array Temperature Calculation
    7. 9.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 9.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 9.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 9.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 9.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application using DLP9000FLS
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
      2. 10.2.2 Typical Application using DLP9000XFLS
  11. 11Power Supply Recommendations
    1. 11.1 DMD Power Supply Requirements
    2. 11.2 DMD Power Supply Power-Up Procedure
    3. 11.3 DMD Power Supply Power-Down Procedure
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General PCB Recommendations
      2. 12.1.2 Power Planes
      3. 12.1.3 LVDS Signals
      4. 12.1.4 Critical Signals
      5. 12.1.5 Flex Connector Plating
      6. 12.1.6 Device Placement
      7. 12.1.7 Device Orientation
      8. 12.1.8 Fiducials
    2. 12.2 Layout Example
      1. 12.2.1 Board Stack and Impedance Requirements
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 器件处理
      2. 13.1.2 器件命名规则
      3. 13.1.3 器件标记
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息
    1. 14.1 热特性
    2. 14.2 封装热阻
    3. 14.3 外壳温度

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Power Supply Recommendations

11.1 DMD Power Supply Requirements

The following power supplies are all required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected. DMD power-up and power-down sequencing is strictly controlled by the DLPC900 or DLPC910 Controllers within their associated reference designs.

CAUTION

For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. VCC, VCCI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and power-down operations. VSS must also be connected. Failure to meet any of the below requirements will result in a significant reduction in the DMD’s reliability and lifetime. Refer to Figure 19.

11.2 DMD Power Supply Power-Up Procedure

  • During power-up, VCC and VCCI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to the DMD.
  • During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended Operating Conditions. During power-up, VBIAS does not have to start after VOFFSET.
  • During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
  • Power supply slew rates requirements during power-up are flexible, provided that the transient voltage levels follow the requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in Figure 19.
  • During power-up, LVCMOS input pins shall not be driven high until after VCC and VCCI have settled at operating voltages listed in Recommended Operating Conditions.

11.3 DMD Power Supply Power-Down Procedure

  • During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the specified limit of ground. Refer to Table 5.
  • During power-down, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended Operating Conditions. During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET.
  • During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS.
  • Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in Figure 19.
  • During power-down, LVCMOS input pins must be less than specified in Recommended Operating Conditions.
DLP9000 Power_Down_Procedure.gif Figure 19. DMD Power Supply Sequencing Requirements
  1. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down.
  2. During power-up, the LVDS signals are less than the input differential voltage (VID) maximum specified in Recommended Operating Conditions. During power-down, LVDS signals are less than the high level input voltage (VIH) maximum specified in Recommended Operating Conditions.
  3. When system power is interrupted, the DLPC900 and the DLPC910 controllers initiate a hardware power-down that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET after the micromirror park sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through software control. For either case, enable signals EN_BIAS, EN_OFFSET, and EN_RESET are used to disable VBIAS, VOFFSET, and VRESET, respectfully.
  4. Refer to Table 5.
  5. Figure not to scale. Details have been omitted for clarity. Refer to Recommended Operating Conditions.

Table 5. DMD Power-Down Sequence Requirements

PARAMETER MIN MAX UNIT
VBIAS Supply voltage level during power–down sequence 4.0 V
VOFFSET 4.0 V
VRESET –4.0 0.5 V