ZHCSKV8A November   2020  – June 2022 DLP670S

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics
    10. 6.10 System Mounting Interface Loads
    11. 6.11 Micromirror Array Physical Characteristics
    12. 6.12 Micromirror Array Optical Characteristics
    13. 6.13 Window Characteristics
    14. 6.14 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
      1. 7.6.1 Micromirror Array Temperature Calculation using Illumination Power Density
      2. 7.6.2 Micromirror Array Temperature Calculation using Total Illumination Power
      3. 7.6.3 Micromirror Array Temperature Calculation using Screen Lumens
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 DMD Die Temperature Sensing
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
    3. 9.3 Restrictions on Hot Plugging and Hot Swapping
      1. 9.3.1 No Hot Plugging
      2. 9.3.2 No Hot Swapping
      3. 9.3.3 Intermittent or Voltage Power Spike Avoidance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Critical Signal Guidelines
      2. 10.1.2 Power Connection Guidelines
      3. 10.1.3 Noise Coupling Avoidance
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by Section 6.4. No level of performance is implied when operating the device above or below Section 6.4 limits.
MIN NOM MAX UNIT
VOLTAGE SUPPLY
VCC LVCMOS logic supply voltage(1) 1.65 1.8 1.95 V
VCCI LVCMOS LVDS Interface supply voltage(1) 1.65 1.8 1.95 V
VOFFSET Mirror electrode and HVCMOS voltage(1)(2) 9.5 10 10.5 V
VBIAS Mirror electrode voltage(1) 17.5 18 18.5 V
VRESET Mirror electrode voltage(1) –14.5 –14 –13.5 V
|VCC – VCCI| Supply voltage delta (absolute value)(3) 0 0.3 V
|VBIAS – VOFFSET| Supply voltage delta (absolute value)(4) 10.5 V
|VBIAS – VRESET| Supply voltage delta (absolute value)(5) 33 V
LVCMOS INTERFACE
VIH(DC) DC input high voltage(6) 0.7 × VCC VCC + 0.3 V
VIL(DC) DC input low voltage(6) –0.3 0.3 × VCC V
VIH(AC) AC input high voltage(6) 0.8 × VCC VCC + 0.3 V
VIL(AC) AC input low voltage(6) –0.3 0.2 × VCC V
tPWRDNZ PWRDNZ pulse width(7) 10 ns
SCP INTERFACE
ƒSCPCLK SCP clock frequency(8) 500 kHz
tSCP_PD Propagation delay, Clock to Q, from rising–edge of SCPCLK to valid SCPDO(9) 0 900 ns
tSCP_NEG_ENZ Time between falling–edge of SCPENZ and the first rising edge of SCPCLK 2 µs
tSCP_POS_ENZ Time between falling–edge of SCPCLK and the rising edge of SCPENZ 2 µs
tSCP_DS SCPDI Clock Setup time (before SCPCLK falling edge)(9) 800 ns
tSCP_DH SCPDI Hold time (after SCPCLK falling edge)(9) 900 ns
tSCP_PW_ENZ SCPENZ inactive pulse width (high level) 2 µs
LVDS INTERFACE
ƒCLOCK Clock frequency for LVDS interface (all channels), DCLK(10) 400 MHz
|VID| Input differential voltage (absolute value)(11) 150 300 440 mV
VCM Common mode voltage(11) 1100 1200 1300 mV
VLVDS LVDS voltage(11) 880 1520 mV
tLVDS_RSTZ Time required for LVDS receivers to recover from PWRDNZ 2000 ns
ZIN Internal differential termination resistance 80 100 120 Ω
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ENVIRONMENTAL
TARRAY Array temperature, long-term operational(12)(13)(14)(15) 10 40 to 70(14) °C
Array temperature, short-term operational(13)(16) 0 10 °C
TWINDOW Window temperature — operational(17) 85 °C
|TDELTA| Absolute Temperature delta between any point on the window edge and the ceramic test point TP1(17)(18) 14 °C
TDP-AVG Average dew point temperature (non-condensing)(19) 28 °C
TDP-ELR Elevated dew point temperature range (non-condensing)(20) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 24 Months
ILLθ Illumination marginal ray angle(21) 55 deg
For Illumination Source Between 420 nm and 700 nm
ILLVIS Illumination power density on array(22) 31 W/cm2
ILLVISTP Illumination total power on array 39.3 W
For Illumination Source <420 nm and >700 nm
ILLIR Illumination Wavelengths > 700 nm 10 mW/cm2
ILLUV Illumination Wavelengths < 420 nm(12) 10 mW/cm2
(1) All voltages are referenced to common ground VSS. VBIAS, VCC, VCCI, VOFFSET, and VRESET power supplies are all required for proper DMD operation. VSS must also be connected.
(2) VOFFSET supply transients must fall within specified max voltages.
(3) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit. See Section 9, Figure 9-1, and Table 9-1.
(4) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. See Section 9, Figure 9-1, and Table 9-1.
(5) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit. See Section 9, Figure 9-1, and Table 9-1.
(6) Tester Conditions for VIH and VIL.
  • Frequency = 60-MHz Maximum Rise Time = 2.5 ns @ (20% – 80%)
  • Frequency = 60-MHz Maximum Fall Time = 2.5 ns @ (80% – 20%)
(7) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.
(8) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. The SCP parameter is related to the frequency of DCLK.
(9) See Figure 6-2.
(10) See the LVDS Timing Requirements in Section 6.8 and Figure 6-6.
(11) See Figure 6-5 LVDS Waveform Requirements.
(12) Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination reduces device lifetime.
(13) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-1 and the package thermal resistance Section 7.6.
(14) Per Figure 6-1, the maximum operational array temperature must be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. See Section 7.7 for a definition of micromirror landed duty cycle.
(15) Long-term is defined as the usable life of the device.
(16) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours.
(17) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4 and TP5 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular application causes another location on the window edge to result in a larger delta temperature, use that location.
(18) DMD is qualified at the maximum temperature specified. Operation of the DMD outside of these limits has not been tested.
(19) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(20) Limit exposure to dew point temperatures in the elevated range during storage and operation to less than a total cumulative time of CTELR.
(21) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including the pond of micromirrors (POM), cannot exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) contributes to thermal limitations described in this document, and may negatively affect lifetime.
(22) The maximum optical power that can be incident on the DMD is limited by the maximum optical power density and the micromirror array temperature.
GUID-96060CB1-2F11-4D59-9BF0-008B0D1BDB3F-low.gif Figure 6-1 Max Recommended Array Temperature—Derating Curve