ZHCSRS7A August   2017  – February 2023 DLP650NE

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Window Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On or Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On or Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
        1.       Application and Implementation
          1. 8.1 Application Information
          2. 8.2 Typical Application
            1. 8.2.1 Design Requirements
            2. 8.2.2 Detailed Design Procedure
  8. 8 Power Supply Requirements
    1. 8.1 DMD Power Supply Requirements
    2. 8.2 DMD Power Supply Power-Up Procedure
    3. 8.3 DMD Power Supply Power-Down Procedure
  9. 9 Device Documentation Support
    1. 9.1 第三方产品免责声明
    2. 9.2 Device Support
      1. 9.2.1 Device Nomenclature
      2. 9.2.2 Device Markings
    3. 9.3 Documentation Support
      1. 9.3.1 Related Documentation
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 支持资源
    6. 9.6 Trademarks
    7. 9.7 静电放电警告
    8. 9.8 术语表
  10. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • FYE|350
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETERTEST CONDITIONS(1)MINTYPMAXUNIT
VOHHigh-level output voltageVCC = 3.3 V, IOH = –20 mA2.4V
VOLLow -level output voltageVCC = 3.45 V, IOL = 15 mA0.4V
IIHHigh-level input current(2)(3)VCC = 3.45 V, VI = VCC250µA
IlLLow-level input currentVCC = 3.45 V, VI = 0–250µA
IOZHigh–impedance output currentVCC = 3.45 V10µA
ICCSupply current(4)VCC = 3.45 V1100mA
ICCIVCCI = 3.45 V500
IOFFSETSupply current(5) VOFFSET = 8.75 V1025mA
IBIASVBIAS = 16.5 V1014
IRESETSupply currentVRESET = –10.5 V1011mA
ITOTALTotal Sum1650
CIInput capacitanceƒ = 1 MHz10pF
COOutput capacitanceƒ = 1 MHz10pF
CMReset group capacitance MBRST(14:0)ƒ = 1 MHz

all inputs interconnected,

(1920 x 1080) array 		330390pF
(1) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
(2) Applies to LVCMOS input pins only; excludes the LVDS pins and MBRST pins
(3) LVCMOS input pins utilize an internal 18000-Ω passive resistor for pullup and pulldown configurations. Refer to Section 5 to determine the pullup or pulldown configuration used.
(4) To prevent excess current, the supply voltage change |VCCI – VCC| must be less than specified limit.
(5) To prevent excess current, the supply voltage change |VBIAS – VOFFSET| must be less than specified limit.