ZHCSNH4B august   2020  – july 2023 DLP471TP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  12. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

GUID-CA0540FD-D0E5-4CDD-9268-20075F742768-low.gif Figure 5-1 FQQ Package270-Pin CLGA(Bottom View)
Table 5-1 Pin Functions
PIN(2) TYPE(1) DESCRIPTION TERMINATION TRACE LENGTH (mm)
NAME PAD ID
D_AP(0) A8 I High-speed Differential Data Pair lane A0 Differential 100 Ω 2.15873
D_AN(0) A7 I High-speed Differential Data Pair lane A0 Differential 100 Ω 2.16135
D_AP(1) B2 I High-speed Differential Data Pair lane A1 Differential 100 Ω 8.33946
D_AN(1) C2 I High-speed Differential Data Pair lane A1 Differential 100 Ω 8.34121
D_AP(2) A6 I High-speed Differential Data Pair lane A2 Differential 100 Ω 6.41271
D_AN(2) A5 I High-speed Differential Data Pair lane A2 Differential 100 Ω 6.41305
D_AP(3) A10 I High-speed Differential Data Pair lane A3 Differential 100 Ω 1.8959
D_AN(3) A9 I High-speed Differential Data Pair lane A3 Differential 100 Ω 1.8959
D_AP(4) D1 I High-speed Differential Data Pair lane A4 Differential 100 Ω 12.11543
D_AN(4) E1 I High-speed Differential Data Pair lane A4 Differential 100 Ω 12.11539
D_AP(5) D3 I High-speed Differential Data Pair lane A5 Differential 100 Ω 12.01561
D_AN(5) E3 I High-speed Differential Data Pair lane A5 Differential 100 Ω 12.0164
D_AP(6) F3 I High-speed Differential Data Pair lane A6 Differential 100 Ω 12.98403
D_AN(6) G3 I High-speed Differential Data Pair lane A6 Differential 100 Ω 12.98177
D_AP(7) A12 I High-speed Differential Data Pair lane A7 Differential 100 Ω 2.29773
D_AN(7) A11 I High-speed Differential Data Pair lane A7 Differential 100 Ω 2.29773
DCLK_AP A3 I High-speed Differential Clock A Differential 100 Ω 11.75367
DCLK_AN A4 I High-speed Differential Clock A Differential 100 Ω 11.57432
D_BP(0) A14 I High-speed Differential Data Pair lane B0 Differential 100 Ω 2.10786
D_BN(0) A15 I High-speed Differential Data Pair lane B0 Differential 100 Ω 2.10711
D_BP(1) F23 I High-speed Differential Data Pair lane B1 Differential 100 Ω 12.79448
D_BN(1) G23 I High-speed Differential Data Pair lane B1 Differential 100 Ω 12.79438
D_BP(2) E24 I High-speed Differential Data Pair lane B2 Differential 100 Ω 13.00876
D_BN(2) E23 I High-speed Differential Data Pair lane B2 Differential 100 Ω 13.00932
D_BP(3) A22 I High-speed Differential Data Pair lane B3 Differential 100 Ω 11.21886
D_BN(3) A23 I High-speed Differential Data Pair lane B3 Differential 100 Ω 11.21881
D_BP(4) D25 I High-speed Differential Data Pair lane B4 Differential 100 Ω 10.79038
D_BN(4) D24 I High-speed Differential Data Pair lane B4 Differential 100 Ω 10.78946
D_BP(5) A20 I High-speed Differential Data Pair lane B5 Differential 100 Ω 5.75986
D_BN(5) A21 I High-speed Differential Data Pair lane B5 Differential 100 Ω 5.75928
D_BP(6) B24 I High-speed Differential Data Pair lane B6 Differential 100 Ω 9.01461
D_BN(6) B25 I High-speed Differential Data Pair lane B6 Differential 100 Ω 9.01416
D_BP(7) A18 I High-speed Differential Data Pair lane B7 Differential 100 Ω 2.08767
D_BN(7) A19 I High-speed Differential Data Pair lane B7 Differential 100 Ω 2.08767
DCLK_BP A17 I High-speed Differential Clock B Differential 100 Ω 2.12928
DCLK_BN A16 I High-speed Differential Clock B Differential 100 Ω 2.30933
LS_WDATA_P T16 I LVDS Data Differential 100 Ω 0
LS_WDATA_N R16 I LVDS Data Differential 100 Ω 0.27407
LS_CLK_P T14 I LVDS CLK Differential 100 Ω 2.43086
LS_CLK_N R14 I LVDS CLK Differential 100 Ω 2.40852
LS_RDATA_A_BISTA R18 O LVCMOS Output 2.00263
BIST_B T20 O LVCMOS Output 4.61261
AMUX_OUT C21 O Analog Test Mux 3.03604
DMUX_OUT R20 O Digital Test Mux 2.88361
DMD_DEN_ARSTZ T18 I ARSTZ 17.5-kΩ pulldown 1.89945
TEMP_N R12 I Temp Diode N 4.02546
TEMP_P T12 I Temp Diode P 3.62598
VDD B13, C5, C9, C12, C15, C18, C22, D6, D7, D14, D16, D19, D20, E21, G21, J4, J21, J23, K3, K22, L2, L4, L22, M1, M3, M21, M23, M25, N2, N4, N6, N8, N16, N18, N20, N22, N24, P3, P5, P7, P9, P11, P13, P15, P17, P19, P21, P23, P25, R2, R4, R6, R8, R10, T3, T5, T7, T9, T11, T13, T15, T17, T19, T21, T23 P Digital core supply voltage Plane
VDDA A24, B3, B5, B7, B9, B11, B14, B16, B18, B20, B22, C1, C24, D4, D23, E2, F4, F22, H3, H22 P HSSI supply voltage Plane
VRESET A2, R1 P Supply voltage for negative bias of micromirror reset signal Plane
VBIAS B1, P1 P Supply voltage for positive bias of micromirror reset signal Plane
VOFFSET A1, A25, T1, T25 P Supply voltage for HVCMOS logic, stepped up logic level Plane
VSS C4, C6, C8, C10, C13, C14, C17, C19, C23, D5, D8, D15, D17, D18, D21, D22, F21, H4, H21, J3, J22, K4, K21, K23, L3, L21, L23, M2, M4, M22, M24, N1, N3, N5, N7, N17, N19, N21, N23, N25, P2, P4, P6, P8, P10, P12, P14, P16, P18, P20, P22, P24, R3, R5, R7, R9, R11, R13, R15, R17, R19, R21, R23, R25, T2, T4, T8, T10 G Ground Plane
VSSA A13, B4, B6, B8, B10, B12, B15, B17, B19, B21, B23, C3, C7, C11, C16, C20, C25, D2, E4, E22, E25, F2, G4, G22, H23 G Ground Plane
DMD_Detect T6 NC DMD detection None
N/C D9, D10, D11, D12, D13, E10, E11, E12, E13, E14, E15, E16, E17, E18, F24, G2, K2, L24, M12, M13, M14, M15, M16, M17, M18, N9, N10, N11, N12, N13, N14, N15, R22, R24 ,T22, T24 NC No connect pin None
(1) I=Input, O=Output, P=Power, G=Ground, NC = No Connect
(2) Only 238 pins are electrically connected for functional use.