ZHCSIP9C July   2018  – May 2022 DLP230KP

PRODUCTION DATA  

  1. 特性
  2. 显示应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics (1)
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Chipset Resources
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
MINNOMMAXUNIT
LPSDR
trRise slew rate(1)(30% to 80%) × VDD, Figure 6-313V/ns
tƒFall slew rate(1)(70% to 20%) × VDD, Figure 6-313V/ns
trRise slew rate(2)(20% to 80%) × VDD, Figure 6-30.25V/ns
tƒFall slew rate(2)(80% to 20%) × VDD, Figure 6-30.25V/ns
tcCycle time LS_CLKFigure 6-27.78.3ns
tW(H)Pulse duration LS_CLK high50% to 50% reference points, Figure 6-23.1ns
tW(L)Pulse duration LS_CLK low50% to 50% reference points, Figure 6-23.1ns
tsuSetup timeLS_WDATA valid before LS_CLK ↑, Figure 6-21.5ns
thHold timeLS_WDATA valid after LS_CLK ↑, Figure 6-21.5ns
tWINDOWWindow time(1) (3)Setup time + hold time, Figure 6-23ns
tDERATINGWindow time derating(1) (3)For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 6-50.35ns
SubLVDS
trRise slew rate20% to 80% reference points, Figure 6-40.71V/ns
tƒFall slew rate80% to 20% reference points, Figure 6-40.71V/ns
tcCycle time DCLKFigure 6-61.791.85ns
tW(H)Pulse duration DCLK high50% to 50% reference points, Figure 6-60.79ns
tW(L)Pulse duration DCLK low50% to 50% reference points, Figure 6-60.79ns
tsuSetup timeD(0:7) valid before
DCLK ↑ or DCLK ↓, Figure 6-6
thHold timeD(0:7) valid after
DCLK ↑ or DCLK ↓, Figure 6-6
tWINDOWWindow timeSetup time + hold time, Figure 6-6, Figure 6-70.3ns
tLVDS-ENABLE+REFGENPower-up receiver(4)2000ns
Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.
Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3.
Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
GUID-BB969F5E-FED3-42CE-8C24-AC40AC255D38-low.gif
Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR)JESD209B.
Figure 6-2 LPSDR Switching Parameters
GUID-353AF840-F97B-4459-ACFF-AFD7F786982F-low.gifFigure 6-3 LPSDR Input Rise and Fall Slew Rate
GUID-EA02EF81-13C8-4720-8A5C-612A0F0E0E19-low.gifFigure 6-4 SubLVDS Input Rise and Fall Slew Rate
GUID-6FD74061-9E7B-424F-99BC-3F8C818A1F22-low.gifFigure 6-5 Window Time Derating Concept
GUID-41F71023-8088-4D50-9BDB-FD3DF56186D1-low.gifFigure 6-6 SubLVDS Switching Parameters
GUID-AC2D165A-DEDC-4DB5-8BF4-AE4ECFBFC530-low.gif
Note: Refer to Section 7.3.3 for details.
Figure 6-7 High-Speed Training Scan Window
GUID-B5C3BD63-4044-42FC-B0E3-81185779A342-low.gifFigure 6-8 SubLVDS Voltage Parameters
GUID-B21DB16E-0F7A-4E25-9247-79DB7F0D0B95-low.gifFigure 6-9 SubLVDS Waveform Parameters
GUID-A0CA1144-5C8C-475C-BD4E-502B8F0BE428-low.gifFigure 6-10 SubLVDS Equivalent Input Circuit
GUID-56923680-876C-4099-B60C-AF51DC860B61-low.gifFigure 6-11 LPSDR Input Hysteresis
GUID-7B52EAD3-43B1-4AC9-8685-10B0E16540B5-low.gifFigure 6-12 LPSDR Read Out
GUID-EF432CDC-064E-4862-9823-9BA35705CA63-low.gif
See Section 7.3.4 for more information.
Figure 6-13 Test Load Circuit for Output Propagation Measurement