ZHCSIP9D july   2018  – july 2023 DLP230KP


  1.   1
  2. 特性
  3. 显示应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Power Density Calculation
    8. 7.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Chipset Resources
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted(1)
Supply voltage VDD Supply voltage for LVCMOS core logic(2)
Supply voltage for LPSDR low speed interface
–0.5 2.3 V
VDDI Supply voltage for SubLVDS receivers(2) –0.5 2.3 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(2) (3) –0.5 11 V
VBIAS Supply voltage for micromirror electrode(2) –0.5 19 V
VRESET Supply voltage for micromirror electrode(2) –15 0.5 V
|VDDI–VDD| Supply voltage delta (absolute value)(4) 0.3 V
|VBIAS–VOFFSET| Supply voltage delta (absolute value)(5) 11 V
|VBIAS–VRESET| Supply voltage delta (absolute value)(6) 34 V
Input voltage Input voltage for other inputs LPSDR(2) –0.5 VDD + 0.5 V
Input voltage for other inputs SubLVDS(2) (7) –0.5 VDDI + 0.5 V
Input pins |VID| SubLVDS input differential voltage (absolute value)(7) 810 mV
IID SubLVDS input differential current 10 mA
Clock frequency ƒclock Clock frequency for low speed interface LS_CLK 130 MHz
ƒclock Clock frequency for high speed interface DCLK 620 MHz
Environmental TARRAY and TWINDOW Temperature – operational (8) –20 90 °C
Temperature – non-operational(8) –40 90 °C
|TDELTA| Absolute temperature delta between any point on the window edge and the ceramic test point TP1(9) 30 °C
TDP Dew Point - operating and non-operating 81 °C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. SubLVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
The highest temperature of the active array (as calculated in Section 7.6) or of any point along the window edge is defined in Figure 7-1. The location of thermal test point TP2 in Figure 7-1 is intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test point TP2 shown in Figure 7-1 is intended to result in the worst case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.