10.1 Layout Guidelines
The DLP230KP DMD is connected to a PCB or a flex circuit using an interposer. For additional layout guidelines regarding length matching, impedance, etc. see the DLPC3434 controller datasheet. For a detailed layout example refer to the layout design files. Some layout guidelines for routing to the DLP230KP DMD are:
- Match lengths for the LS_WDATA and LS_CLK signals.
- Minimize vias, layer changes, and turns for the HS bus signals. Refer to Figure 24.
- Minimum of two 100-nF (25 V) capacitors - one close to VBIAS pin. Capacitors C4 and C8 in Figure 24.
- Minimum of two 100-nF (25 V) capacitors - one close to each VRST pin. Capacitors C3 and C7 in Figure 24.
- Minimum of two 220-nF (25 V) capacitors - one close to each VOFS pin. Capacitors C5 and C6 in Figure 24.
- Minimum of four 100-nF (6.3 V) capacitors - two close to each side of the DMD. Capacitors C1, C2, C9 and C10 in Figure 24.