DLPS119B December   2018  – May 2022 DLP2010NIR

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
      1. 6.13.1 Software Requirements
    14. 6.14 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • FQJ|40
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

GUID-7936A0D5-77B9-4CA4-8C08-6F52610A1D41-low.gif Figure 5-1 FQJ Package. 40-Pin CLGA. Bottom View.
PIN TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET TRACE LENGTH(2) (mm)
NAME NO.
DATA INPUTS, SUBLVDS INTERFACE
D_N(0) G4 I SubLVDS Double Input data pair 0, negative 7.03
D_P(0) G3 I SubLVDS Double Input data pair 0, positive 7.03
D_N(1) G8 I SubLVDS Double Input data pair 1, negative 7.03
D_P(1) G7 I SubLVDS Double Input data pair 1, positive 7.03
D_N(2) H5 I SubLVDS Double Input data pair 2, negative 7.02
D_P(2) H6 I SubLVDS Double Input data pair 2, positive 7.02
D_N(3) H1 I SubLVDS Double Input data pair 3, negative 7.00
D_P(3) H2 I SubLVDS Double Input data pair 3, positive 7.00
DCLK_N H9 I SubLVDS Double Clock, negative 7.03
DCLK_P H10 I SubLVDS Double Clock, positive 7.03
CONTROL INPUTS, LPSDR INTERFACE
DMD_DEN_ARSTZ G12 I LPSDR (1) Active low asynchronous DMD reset signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 5.72
LS_CLK G19 I LPSDR Single Clock for low-speed interface 3.54
LS_WDATA G18 I LPSDR Single Write data for low-speed interface 3.54
LS_RDATA G11 O LPSDR Single Read data for low-speed interface 8.11
POWER
VBIAS (3) H17 Power Supply voltage for micromirror positive bias level
VOFFSET (3) H13 Power Supply voltage for high voltage CMOS (HVCMOS) core logic.
Includes: Supply voltage for stepped high level at micromirror address electrodes and supply voltage for offset level at micromirrors.
VRESET (3) H18 Power Supply voltage for micromirror negative reset level
VDD(3) G20 Power Supply voltage for low voltage CMOS (LVCMOS) core logic. Includes supply voltage for LPSDR inputs and supply voltage for normal high level at micromirror address electrodes.
VDD H14 Power
VDD H15 Power
VDD H16 Power
VDD H19 Power
VDD H20 Power
VDDI (3) G1 Power Supply voltage for SubLVDS receivers
VDDI G2 Power
VDDI G5 Power
VDDI G6 Power
VSS(3) G9 Power Ground. Common return for all power.
VSS G10 Power
VSS G13 Power
VSS G14 Power
VSS G15 Power
VSS G16 Power
VSS G17 Power
VSS H3 Power
VSS H4 Power
VSS H7 Power
VSS H8 Power
VSS H11 Power
VSS H12 Power
RESERVED
No connect A2, A3, A4, A5, A6 A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19 Reserved pins. For proper device operation, leave these pins unconnected.
No connect B2, B3, B17, B18 Reserved pins. For proper device operation, leave these pins unconnected.
No connect C2, C3, C17, C18 Reserved pins. For proper device operation, leave these pins unconnected.
No connect D2, D3, D17, D18 Reserved pins. For proper device operation, leave these pins unconnected.
No connect E2, E3, E17, E18 Reserved pins. For proper device operation, leave these pins unconnected.
No connect F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19 Reserved pins. For proper device operation, leave these pins unconnected.
(1) Low speed interface is LPSDR and adheres to the electrical characteristics and AC/DC operating conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQJ ceramic package is 9.8.
Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.