ZHCSQ74A September   2022  – November 2022 DAC82001

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 DAC Transfer Function
        2. 7.3.1.2 DAC Register Structure
      2. 7.3.2 Power-On Reset (POR)
      3. 7.3.3 Hardware Reset
      4. 7.3.4 Software Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
        1. 7.5.1.1 SYNC Interrupt
    6. 7.6 Register Maps
      1. 7.6.1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Arbitrary Waveform Generator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Bipolar Analog Output Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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5 Pin Configuration and Functions

Figure 5-1 DRX (10-Pin WSON) Package, Top View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
AGND 4 Ground Ground reference point for all circuitry on the device.
NC 9 — Do not connect
RESET 5 Input Asynchronous reset. Active low. If RESET is low, all DAC channels reset either to zero-scale (RSTSEL = AGND) or to midscale (RSTSEL = VDD).
RSTSEL 3 Input Reset select pin.
DAC powers up to zero scale if RSTSEL = AGND.
DAC powers up to midscale if RSTSEL = VDD.
SCLK 6 Input Serial interface clock of SPI.
SDIN 8 Input Serial interface data input of SPI. Data are clocked into the input shift register on each falling edge of the SCLK pin.
SYNC 7 Input Serial data enable of SPI. Active low. This input is the frame-synchronization signal for the serial data. When the signal goes low, the serial interface input shift register is enabled.
VDD 1 Power Analog supply voltage (2.7 V to 5.5 V)
VOUT 2 Output Analog output voltage from DAC
VREF 10 Input This pin is the external reference input to the device.