ZHCSLN9A October   2020  – May 2021 DAC61402 , DAC81402

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 7.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 7.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 7.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 7.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 7.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 R-2R Ladder DAC
      2. 8.3.2 Programmable-Gain Output Buffer
        1. 8.3.2.1 Sense Pins
      3. 8.3.3 DAC Register Structure
        1. 8.3.3.1 DAC Output Update
          1. 8.3.3.1.1 Synchronous Update
          2. 8.3.3.1.2 Asynchronous Update
        2. 8.3.3.2 Broadcast DAC Register
        3. 8.3.3.3 Clear DAC Operation
      4. 8.3.4 Internal Reference
      5. 8.3.5 Power-On Reset (POR)
        1. 8.3.5.1 Hardware Reset
        2. 8.3.5.2 Software Reset
      6. 8.3.6 Thermal Alarm
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Map
      1. 8.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 8.6.2  DEVICEID Register (address = 01h) [reset = 0A70h or 0930h]
      3. 8.6.3  STATUS Register (address = 02h) [reset = 0000h]
      4. 8.6.4  SPICONFIG Register (address = 03h) [reset = 0AA4h]
      5. 8.6.5  GENCONFIG Register (address = 04h) [reset = 4000h]
      6. 8.6.6  BRDCONFIG Register (address = 05h) [reset = 000Fh]
      7. 8.6.7  SYNCCONFIG Register (address = 06h) [reset = 0000h]
      8. 8.6.8  DACPWDWN Register (address = 09h) [reset = FFFFh]
      9. 8.6.9  DACRANGE Register (address = 0Ah) [reset = 0000h]
      10. 8.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]
      11. 8.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]
      12. 8.6.12 DACn Register (address = 11h to 12h) [reset = 0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.13 Typical Characteristics

at TA = 25°C, DVDD = 5.0 V, IOVDD = 1.8 V, internal reference enabled, unipolar ranges: AVSS = 0 V and AVDD ≥ VMAX + 1.5 V for the DAC range, bipolar ranges: AVSS ≤ VMIN − 1.5 V and AVDD ≥ VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless otherwise noted)

 
Figure 7-3 DAC81402 INL vs Digital Input Code
(Bipolar Outputs)
 
Figure 7-5 DAC81402 DNL vs Digital Input Code
(Bipolar Outputs)
 
Figure 7-7 DAC81402 TUE vs Digital Input Code
(Bipolar Outputs)
 
Figure 7-9 DAC61402 INL vs Digital Input Code
(Bipolar Outputs)
 
Figure 7-11 DAC61402 DNL vs Digital Input Code
(Bipolar Outputs)
 
Figure 7-13 DAC61402 TUE vs Digital Input Code
(Bipolar Outputs)
 
Figure 7-15 DAC81402 INL vs Temperature
 
Figure 7-17 DAC61402 INL vs Temperature
 
Figure 7-19 TUE vs Temperature
 
Figure 7-21 Unipolar Zero Code Error vs Temperature
 
Figure 7-23 Bipolar Zero Error vs Temperature
 
Figure 7-25 Full-Scale Error vs Temperature
 
Figure 7-27 Supply Current (AIDD, AISS)
vs Digital Input Code
DAC range: ±20 V
Figure 7-29 Supply Current vs Temperature
 
Figure 7-31 Headroom and Footroom from Supply
vs Output Current
DAC range: ±10 V
Figure 7-33 Full-Scale Settling Time, Rising Edge
DAC range: ±20 V
Figure 7-35 DAC Output Enable Glitch
DAC range: ±10 V
Figure 7-37 Glitch Impulse, 1 LSB Step,
Falling Edge
 
Figure 7-39 Power-Down Response
DAC range: 0 V to 5 V, midscale code
Figure 7-41 DAC Output Noise Density vs Frequency
 
Figure 7-43 Internal Reference Voltage vs Temperature
 
Figure 7-45 Internal Reference Voltage vs Time
 
Figure 7-47 Internal Reference Noise
 
Figure 7-4 DAC81402 INL vs Digital Input Code
(Unipolar Outputs)
 
Figure 7-6 DAC81402 DNL vs Digital Input Code
(Unipolar Outputs)
 
Figure 7-8 DAC81402 TUE vs Digital Input Code
(Unipolar Outputs)
 
Figure 7-10 DAC61402 INL vs Digital Input Code
(Unipolar Outputs)
 
Figure 7-12 DAC61402 DNL vs Digital Input Code
(Unipolar Outputs)
 
Figure 7-14 DAC61402 TUE vs Digital Input Code
(Unipolar Outputs)
 
Figure 7-16 DAC81402 DNL vs Temperature
 
Figure 7-18 DAC61402 DNL vs Temperature
 
Figure 7-20 Unipolar Offset Error vs Temperature
 
Figure 7-22 Bipolar Zero Code Error vs Temperature
 
Figure 7-24 Gain Error vs Temperature
 
Figure 7-26 Supply Current (DIDD)
vs Digital Input Code
 
Figure 7-28 Supply Current (IIOVDD)
vs Supply Voltage
DAC range: ±20 V
Figure 7-30 Power-Down Current vs Temperature
 
Figure 7-32 Source and Sink Capability
DAC range: ±10 V
Figure 7-34 Full-Scale Settling Time, Falling Edge
DAC range: ±10 V
Figure 7-36 Glitch Impulse, 1 LSB Step,
Rising Edge
 
Figure 7-38 Power-Up Response
DAC range: ±20 V
Figure 7-40 Clear Command Response
DAC range: 0 V to 5 V, midscale code
Figure 7-42 DAC Output Noise
 
Figure 7-44 Internal Reference Voltage
vs Supply Voltage
 
Figure 7-46 Internal Reference Noise Density vs Frequency
 
Figure 7-48 Internal Reference Temperature Drift Histogram