ZHCSHU4E April 2005 – March 2018 DAC7811
PRODUCTION DATA.
The DAC7811 has a 3-wire serial interface (SYNC, SCLK, and SDIN), which is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most Digital Signal Processor (DSP) devices. See the Serial Write Operation timing diagram (Figure 27) for an example of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making the DAC7811 compatible with high-speed DSPs. The SDIN and SCLK input buffers are gated off while SYNC is high which minimizes the power dissipation of the digital interface. After SYNC goes low, the digital interface will respond to the SDIN and SCLK input signals and data can now be shifted into the device. If an inactive clock edge occurs after SYNC goes low, but before the first active clock edge, it will be ignored. If the SDO pin is being used then SYNC must remain low until after the inactive clock edge that follows the 16th active clock edge.