ZHCSM85A October   2020  – September 2023 DAC43701-Q1 , DAC53701-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast-Mode Plus
    9. 6.9  Timing Requirements: GPI
    10. 6.10 Timing Diagram
    11. 6.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 6.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 6.13 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 Reference Selection and DAC Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 General-Purpose Input (GPI)
      3. 7.3.3 DAC Update
        1. 7.3.3.1 DAC Update Busy
      4. 7.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check
        2. 7.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 7.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 7.3.5 Programmable Slew Rate
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 Software Reset
      8. 7.3.8 Device Lock Feature
      9. 7.3.9 PMBus Compatibility
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
      2. 7.4.2 Continuous Waveform Generation (CWG) Mode
      3. 7.4.3 PMBus Compatibility Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
        1. 7.5.2.1 Address Byte
          1. 7.5.2.1.1 Target Address Configuration
        2. 7.5.2.2 Command Byte
      3. 7.5.3 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 7.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 7.6.3  CONFIG2 Register (address = D2h) [reset = device-specific]
      4. 7.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 7.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 7.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = device-specific]
      7. 7.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset =device-specific]
      8. 7.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 7.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 7.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Power-Supply Margining
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LED Thermal Foldback
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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Programming

The DACx3701-Q1 devices have a 2-wire serial interface, SCL and SDA (see the pin diagram in Section 5). The I2C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through the open drain I/O pins, SDA and SCL.

The I2C specification states that the device that controls communication is called a controller, and the devices that are controlled by the controller are called targets. The controller device generates the SCL signal. The controller device also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus to indicate the start or stop of a data transfer. Device addressing is completed by the controller. The controller device on an I2C bus is typically a microcontroller or digital signal processor (DSP). The DACx3701-Q1 family operates as a target device on the I2C bus. A target device acknowledges controller commands, and upon controller control, receives or transmits data.

Typically, theDACx3701-Q1 family operates as a target receiver. A controller device writes to the DACx3701-Q1, a target receiver. However, if a controller device requires the DACx3701-Q1 internal register data, the DACx3701-Q1 operate as a target transmitter. In this case, the controller device reads from the DACx3701-Q1. According to I2C terminology, read and write refer to the controller device.

The DACx3701-Q1 family is a target and supports the following data transfer modes:

  • Standard mode (100Kbps)
  • Fast mode (400Kbps)
  • Fast-mode plus (1.0Mbps)

The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred to as F/S-mode in this document. The fast-mode plus protocol is supported in terms of data transfer speed, but not output current. The low-level output current is 3 mA; similar to the case of standard and fast modes. The DACx3701-Q1 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports the general call reset function. Sending the following sequence initiates a software reset within the device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the ACK bit, following the second byte.

Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during the high period of the ninth clock cycle. Figure 7-3 shows that a not-acknowledge is when the SDA line is left high during the high period of the ninth clock cycle.

GUID-20211130-SS0I-WJVK-SQZ5-V6KZDFVZF0MG-low.svg Figure 7-3 Acknowledge and Not Acknowledge on the I2C Bus